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34 #include "rte_cpuflags.h"
48 typedef uint32_t cpuid_registers_t[4];
51 * Struct to hold a processor feature entry
53 struct feature_entry {
54 uint32_t leaf; /**< cpuid leaf */
55 uint32_t subleaf; /**< cpuid subleaf */
56 uint32_t reg; /**< cpuid register */
57 uint32_t bit; /**< cpuid register bit */
58 #define CPU_FLAG_NAME_MAX_LEN 64
59 char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
62 #define FEAT_DEF(name, leaf, subleaf, reg, bit) \
63 [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
65 const struct feature_entry rte_cpu_feature_table[] = {
66 FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0)
67 FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1)
68 FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2)
69 FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX, 3)
70 FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX, 4)
71 FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX, 5)
72 FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX, 6)
73 FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX, 7)
74 FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX, 8)
75 FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX, 9)
76 FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10)
77 FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12)
78 FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13)
79 FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14)
80 FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15)
81 FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17)
82 FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18)
83 FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19)
84 FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20)
85 FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21)
86 FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22)
87 FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23)
88 FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24)
89 FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25)
90 FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26)
91 FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27)
92 FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28)
93 FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29)
94 FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30)
96 FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX, 0)
97 FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX, 1)
98 FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX, 2)
99 FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX, 3)
100 FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX, 4)
101 FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX, 5)
102 FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX, 6)
103 FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX, 7)
104 FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX, 8)
105 FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX, 9)
106 FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11)
107 FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12)
108 FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13)
109 FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14)
110 FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15)
111 FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16)
112 FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17)
113 FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18)
114 FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19)
115 FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21)
116 FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22)
117 FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23)
118 FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24)
119 FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25)
120 FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26)
121 FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27)
122 FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28)
123 FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29)
124 FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31)
126 FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX, 0)
127 FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX, 1)
128 FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX, 2)
129 FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX, 4)
130 FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX, 5)
131 FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX, 6)
133 FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX, 0)
134 FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX, 1)
135 FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3)
137 FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0)
138 FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2)
139 FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4)
140 FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5)
141 FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6)
142 FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7)
143 FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8)
144 FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
145 FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
146 FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)
148 FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)
149 FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)
151 FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)
152 FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20)
153 FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26)
154 FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27)
155 FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
157 FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8)
161 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
163 const struct feature_entry *feat;
164 cpuid_registers_t regs;
165 unsigned int maxleaf;
167 if (feature >= RTE_CPUFLAG_NUMFLAGS)
168 /* Flag does not match anything in the feature tables */
171 feat = &rte_cpu_feature_table[feature];
174 /* This entry in the table wasn't filled out! */
177 maxleaf = __get_cpuid_max(feat->leaf & 0x80000000, NULL);
179 if (maxleaf < feat->leaf)
182 __cpuid_count(feat->leaf, feat->subleaf,
183 regs[RTE_REG_EAX], regs[RTE_REG_EBX],
184 regs[RTE_REG_ECX], regs[RTE_REG_EDX]);
186 /* check if the feature is enabled */
187 return (regs[feat->reg] >> feat->bit) & 1;
191 rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
193 if (feature >= RTE_CPUFLAG_NUMFLAGS)
195 return rte_cpu_feature_table[feature].name;