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23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
35 * Copyright (c) 2008 Marcel Moolenaar
36 * Copyright (c) 2001 Benno Rice
37 * Copyright (c) 2001 David E. O'Brien
38 * Copyright (c) 1998 Doug Rabson
39 * All rights reserved.
42 #ifndef _RTE_ATOMIC_PPC_64_H_
43 #define _RTE_ATOMIC_PPC_64_H_
50 #include "generic/rte_atomic.h"
53 * General memory barrier.
55 * Guarantees that the LOAD and STORE operations generated before the
56 * barrier occur before the LOAD and STORE operations generated after.
58 #define rte_mb() asm volatile("sync" : : : "memory")
61 * Write memory barrier.
63 * Guarantees that the STORE operations generated before the barrier
64 * occur before the STORE operations generated after.
67 #define rte_wmb() asm volatile("lwsync" : : : "memory")
69 #define rte_wmb() asm volatile("sync" : : : "memory")
73 * Read memory barrier.
75 * Guarantees that the LOAD operations generated before the barrier
76 * occur before the LOAD operations generated after.
79 #define rte_rmb() asm volatile("lwsync" : : : "memory")
81 #define rte_rmb() asm volatile("sync" : : : "memory")
84 #define rte_smp_mb() rte_mb()
86 #define rte_smp_wmb() rte_wmb()
88 #define rte_smp_rmb() rte_rmb()
90 /*------------------------- 16 bit atomic operations -------------------------*/
91 /* To be compatible with Power7, use GCC built-in functions for 16 bit
94 #ifndef RTE_FORCE_INTRINSICS
96 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
98 return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,
99 __ATOMIC_ACQUIRE) ? 1 : 0;
102 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
104 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
108 rte_atomic16_inc(rte_atomic16_t *v)
110 __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
114 rte_atomic16_dec(rte_atomic16_t *v)
116 __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
119 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
121 return __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
124 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
126 return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
129 /*------------------------- 32 bit atomic operations -------------------------*/
132 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
134 unsigned int ret = 0;
138 "1:\tlwarx %[ret], 0, %[dst]\n"
139 "cmplw %[exp], %[ret]\n"
141 "stwcx. %[src], 0, %[dst]\n"
146 "stwcx. %[ret], 0, %[dst]\n"
150 : [ret] "=&r" (ret), "=m" (*dst)
160 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
162 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
166 rte_atomic32_inc(rte_atomic32_t *v)
171 "1: lwarx %[t],0,%[cnt]\n"
172 "addic %[t],%[t],1\n"
173 "stwcx. %[t],0,%[cnt]\n"
175 : [t] "=&r" (t), "=m" (v->cnt)
176 : [cnt] "r" (&v->cnt), "m" (v->cnt)
177 : "cc", "xer", "memory");
181 rte_atomic32_dec(rte_atomic32_t *v)
186 "1: lwarx %[t],0,%[cnt]\n"
187 "addic %[t],%[t],-1\n"
188 "stwcx. %[t],0,%[cnt]\n"
190 : [t] "=&r" (t), "=m" (v->cnt)
191 : [cnt] "r" (&v->cnt), "m" (v->cnt)
192 : "cc", "xer", "memory");
195 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
201 "1: lwarx %[ret],0,%[cnt]\n"
202 "addic %[ret],%[ret],1\n"
203 "stwcx. %[ret],0,%[cnt]\n"
207 : [cnt] "r" (&v->cnt)
208 : "cc", "xer", "memory");
213 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
219 "1: lwarx %[ret],0,%[cnt]\n"
220 "addic %[ret],%[ret],-1\n"
221 "stwcx. %[ret],0,%[cnt]\n"
225 : [cnt] "r" (&v->cnt)
226 : "cc", "xer", "memory");
230 /*------------------------- 64 bit atomic operations -------------------------*/
233 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
235 unsigned int ret = 0;
239 "1: ldarx %[ret], 0, %[dst]\n"
240 "cmpld %[exp], %[ret]\n"
242 "stdcx. %[src], 0, %[dst]\n"
247 "stdcx. %[ret], 0, %[dst]\n"
251 : [ret] "=&r" (ret), "=m" (*dst)
261 rte_atomic64_init(rte_atomic64_t *v)
266 static inline int64_t
267 rte_atomic64_read(rte_atomic64_t *v)
271 asm volatile("ld%U1%X1 %[ret],%[cnt]"
273 : [cnt] "m"(v->cnt));
279 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
281 asm volatile("std%U0%X0 %[new_value],%[cnt]"
283 : [new_value] "r"(new_value));
287 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
292 "1: ldarx %[t],0,%[cnt]\n"
293 "add %[t],%[inc],%[t]\n"
294 "stdcx. %[t],0,%[cnt]\n"
296 : [t] "=&r" (t), "=m" (v->cnt)
297 : [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
302 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
307 "1: ldarx %[t],0,%[cnt]\n"
308 "subf %[t],%[dec],%[t]\n"
309 "stdcx. %[t],0,%[cnt]\n"
311 : [t] "=&r" (t), "+m" (v->cnt)
312 : [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
317 rte_atomic64_inc(rte_atomic64_t *v)
322 "1: ldarx %[t],0,%[cnt]\n"
323 "addic %[t],%[t],1\n"
324 "stdcx. %[t],0,%[cnt]\n"
326 : [t] "=&r" (t), "+m" (v->cnt)
327 : [cnt] "r" (&v->cnt), "m" (v->cnt)
328 : "cc", "xer", "memory");
332 rte_atomic64_dec(rte_atomic64_t *v)
337 "1: ldarx %[t],0,%[cnt]\n"
338 "addic %[t],%[t],-1\n"
339 "stdcx. %[t],0,%[cnt]\n"
341 : [t] "=&r" (t), "+m" (v->cnt)
342 : [cnt] "r" (&v->cnt), "m" (v->cnt)
343 : "cc", "xer", "memory");
346 static inline int64_t
347 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
353 "1: ldarx %[ret],0,%[cnt]\n"
354 "add %[ret],%[inc],%[ret]\n"
355 "stdcx. %[ret],0,%[cnt]\n"
359 : [inc] "r" (inc), [cnt] "r" (&v->cnt)
365 static inline int64_t
366 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
372 "1: ldarx %[ret],0,%[cnt]\n"
373 "subf %[ret],%[dec],%[ret]\n"
374 "stdcx. %[ret],0,%[cnt]\n"
378 : [dec] "r" (dec), [cnt] "r" (&v->cnt)
384 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
390 "1: ldarx %[ret],0,%[cnt]\n"
391 "addic %[ret],%[ret],1\n"
392 "stdcx. %[ret],0,%[cnt]\n"
396 : [cnt] "r" (&v->cnt)
397 : "cc", "xer", "memory");
402 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
408 "1: ldarx %[ret],0,%[cnt]\n"
409 "addic %[ret],%[ret],-1\n"
410 "stdcx. %[ret],0,%[cnt]\n"
414 : [cnt] "r" (&v->cnt)
415 : "cc", "xer", "memory");
420 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
422 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
426 * Atomically set a 64-bit counter to 0.
429 * A pointer to the atomic counter.
431 static inline void rte_atomic64_clear(rte_atomic64_t *v)
441 #endif /* _RTE_ATOMIC_PPC_64_H_ */