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36 #include <linux/pci_regs.h>
37 #include <sys/eventfd.h>
38 #include <sys/socket.h>
39 #include <sys/ioctl.h>
44 #include <rte_eal_memconfig.h>
45 #include <rte_malloc.h>
47 #include "eal_filesystem.h"
48 #include "eal_pci_init.h"
50 #include "eal_private.h"
54 * PCI probing under linux (VFIO version)
56 * This code tries to determine if the PCI device is bound to VFIO driver,
57 * and initialize it (map BARs, set up interrupts) if that's the case.
59 * This file is only compiled if CONFIG_RTE_EAL_VFIO is set to "y".
64 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
65 #define PAGE_MASK (~(PAGE_SIZE - 1))
67 static struct rte_tailq_elem rte_vfio_tailq = {
68 .name = "VFIO_RESOURCE_LIST",
70 EAL_REGISTER_TAILQ(rte_vfio_tailq)
73 pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
74 void *buf, size_t len, off_t offs)
76 return pread64(intr_handle->vfio_dev_fd, buf, len,
77 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
81 pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
82 const void *buf, size_t len, off_t offs)
84 return pwrite64(intr_handle->vfio_dev_fd, buf, len,
85 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
88 /* get PCI BAR number where MSI-X interrupts are */
90 pci_vfio_get_msix_bar(int fd, int *msix_bar, uint32_t *msix_table_offset,
91 uint32_t *msix_table_size)
96 uint8_t cap_id, cap_offset;
98 /* read PCI capability pointer from config space */
99 ret = pread64(fd, ®, sizeof(reg),
100 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
101 PCI_CAPABILITY_LIST);
102 if (ret != sizeof(reg)) {
103 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
108 /* we need first byte */
109 cap_offset = reg & 0xFF;
113 /* read PCI capability ID */
114 ret = pread64(fd, ®, sizeof(reg),
115 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
117 if (ret != sizeof(reg)) {
118 RTE_LOG(ERR, EAL, "Cannot read capability ID from PCI "
123 /* we need first byte */
126 /* if we haven't reached MSI-X, check next capability */
127 if (cap_id != PCI_CAP_ID_MSIX) {
128 ret = pread64(fd, ®, sizeof(reg),
129 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
131 if (ret != sizeof(reg)) {
132 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
137 /* we need second byte */
138 cap_offset = (reg & 0xFF00) >> 8;
142 /* else, read table offset */
144 /* table offset resides in the next 4 bytes */
145 ret = pread64(fd, ®, sizeof(reg),
146 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
148 if (ret != sizeof(reg)) {
149 RTE_LOG(ERR, EAL, "Cannot read table offset from PCI config "
154 ret = pread64(fd, &flags, sizeof(flags),
155 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
157 if (ret != sizeof(flags)) {
158 RTE_LOG(ERR, EAL, "Cannot read table flags from PCI config "
163 *msix_bar = reg & RTE_PCI_MSIX_TABLE_BIR;
164 *msix_table_offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;
165 *msix_table_size = 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));
173 /* set PCI bus mastering */
175 pci_vfio_set_bus_master(int dev_fd)
180 ret = pread64(dev_fd, ®, sizeof(reg),
181 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
183 if (ret != sizeof(reg)) {
184 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
188 /* set the master bit */
189 reg |= PCI_COMMAND_MASTER;
191 ret = pwrite64(dev_fd, ®, sizeof(reg),
192 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
195 if (ret != sizeof(reg)) {
196 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
203 /* set up interrupt support (but not enable interrupts) */
205 pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
207 int i, ret, intr_idx;
209 /* default to invalid index */
210 intr_idx = VFIO_PCI_NUM_IRQS;
212 /* get interrupt type from internal config (MSI-X by default, can be
213 * overriden from the command line
215 switch (internal_config.vfio_intr_mode) {
216 case RTE_INTR_MODE_MSIX:
217 intr_idx = VFIO_PCI_MSIX_IRQ_INDEX;
219 case RTE_INTR_MODE_MSI:
220 intr_idx = VFIO_PCI_MSI_IRQ_INDEX;
222 case RTE_INTR_MODE_LEGACY:
223 intr_idx = VFIO_PCI_INTX_IRQ_INDEX;
225 /* don't do anything if we want to automatically determine interrupt type */
226 case RTE_INTR_MODE_NONE:
229 RTE_LOG(ERR, EAL, " unknown default interrupt type!\n");
233 /* start from MSI-X interrupt type */
234 for (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {
235 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
238 /* skip interrupt modes we don't want */
239 if (internal_config.vfio_intr_mode != RTE_INTR_MODE_NONE &&
245 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
247 RTE_LOG(ERR, EAL, " cannot get IRQ info, "
248 "error %i (%s)\n", errno, strerror(errno));
252 /* if this vector cannot be used with eventfd, fail if we explicitly
253 * specified interrupt type, otherwise continue */
254 if ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {
255 if (internal_config.vfio_intr_mode != RTE_INTR_MODE_NONE) {
257 " interrupt vector does not support eventfd!\n");
263 /* set up an eventfd for interrupts */
264 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
266 RTE_LOG(ERR, EAL, " cannot set up eventfd, "
267 "error %i (%s)\n", errno, strerror(errno));
271 dev->intr_handle.fd = fd;
272 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
275 case VFIO_PCI_MSIX_IRQ_INDEX:
276 internal_config.vfio_intr_mode = RTE_INTR_MODE_MSIX;
277 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
279 case VFIO_PCI_MSI_IRQ_INDEX:
280 internal_config.vfio_intr_mode = RTE_INTR_MODE_MSI;
281 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
283 case VFIO_PCI_INTX_IRQ_INDEX:
284 internal_config.vfio_intr_mode = RTE_INTR_MODE_LEGACY;
285 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
288 RTE_LOG(ERR, EAL, " unknown interrupt type!\n");
295 /* if we're here, we haven't found a suitable interrupt vector */
300 * map the PCI resources of a PCI device in virtual memory (VFIO version).
301 * primary and secondary processes follow almost exactly the same path
304 pci_vfio_map_resource(struct rte_pci_device *dev)
306 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
307 char pci_addr[PATH_MAX] = {0};
309 struct rte_pci_addr *loc = &dev->addr;
310 int i, ret, msix_bar;
311 struct mapped_pci_resource *vfio_res = NULL;
312 struct mapped_pci_res_list *vfio_res_list = RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
314 struct pci_map *maps;
315 uint32_t msix_table_offset = 0;
316 uint32_t msix_table_size = 0;
319 dev->intr_handle.fd = -1;
320 dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
322 /* store PCI address string */
323 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
324 loc->domain, loc->bus, loc->devid, loc->function);
326 if ((ret = vfio_setup_device(pci_get_sysfs_path(), pci_addr,
327 &vfio_dev_fd, &device_info)))
330 /* get MSI-X BAR, if any (we have to know where it is because we can't
331 * easily mmap it when using VFIO) */
333 ret = pci_vfio_get_msix_bar(vfio_dev_fd, &msix_bar,
334 &msix_table_offset, &msix_table_size);
336 RTE_LOG(ERR, EAL, " %s cannot get MSI-X BAR number!\n", pci_addr);
341 /* if we're in a primary process, allocate vfio_res and get region info */
342 if (internal_config.process_type == RTE_PROC_PRIMARY) {
343 vfio_res = rte_zmalloc("VFIO_RES", sizeof(*vfio_res), 0);
344 if (vfio_res == NULL) {
346 "%s(): cannot store uio mmap details\n", __func__);
350 memcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));
352 /* get number of registers (up to BAR5) */
353 vfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,
354 VFIO_PCI_BAR5_REGION_INDEX + 1);
356 /* if we're in a secondary process, just find our tailq entry */
357 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
358 if (rte_eal_compare_pci_addr(&vfio_res->pci_addr,
363 /* if we haven't found our tailq entry, something's wrong */
364 if (vfio_res == NULL) {
365 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
373 maps = vfio_res->maps;
375 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
376 struct vfio_region_info reg = { .argsz = sizeof(reg) };
379 unsigned long offset, size;
384 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®);
387 RTE_LOG(ERR, EAL, " %s cannot get device region info "
388 "error %i (%s)\n", pci_addr, errno, strerror(errno));
390 if (internal_config.process_type == RTE_PROC_PRIMARY)
395 /* chk for io port region */
396 ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
397 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)
398 + PCI_BASE_ADDRESS_0 + i*4);
400 if (ret != sizeof(ioport_bar)) {
402 "Cannot read command (%x) from config space!\n",
403 PCI_BASE_ADDRESS_0 + i*4);
407 if (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) {
409 "Ignore mapping IO port bar(%d) addr: %x\n",
414 /* skip non-mmapable BARs */
415 if ((reg.flags & VFIO_REGION_INFO_FLAG_MMAP) == 0)
420 * VFIO will not let us map the MSI-X table,
421 * but we can map around it.
423 uint32_t table_start = msix_table_offset;
424 uint32_t table_end = table_start + msix_table_size;
425 table_end = (table_end + ~PAGE_MASK) & PAGE_MASK;
426 table_start &= PAGE_MASK;
428 if (table_start == 0 && table_end >= reg.size) {
429 /* Cannot map this BAR */
430 RTE_LOG(DEBUG, EAL, "Skipping BAR %d\n", i);
433 memreg[0].offset = reg.offset;
434 memreg[0].size = table_start;
435 memreg[1].offset = reg.offset + table_end;
436 memreg[1].size = reg.size - table_end;
439 "Trying to map BAR %d that contains the MSI-X "
440 "table. Trying offsets: "
441 "0x%04lx:0x%04lx, 0x%04lx:0x%04lx\n", i,
442 memreg[0].offset, memreg[0].size,
443 memreg[1].offset, memreg[1].size);
446 memreg[0].offset = reg.offset;
447 memreg[0].size = reg.size;
450 /* try to figure out an address */
451 if (internal_config.process_type == RTE_PROC_PRIMARY) {
452 /* try mapping somewhere close to the end of hugepages */
453 if (pci_map_addr == NULL)
454 pci_map_addr = pci_find_max_end_va();
456 bar_addr = pci_map_addr;
457 pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg.size);
459 bar_addr = maps[i].addr;
462 /* reserve the address using an inaccessible mapping */
463 bar_addr = mmap(bar_addr, reg.size, 0, MAP_PRIVATE |
464 MAP_ANONYMOUS, -1, 0);
465 if (bar_addr != MAP_FAILED) {
466 void *map_addr = NULL;
467 if (memreg[0].size) {
468 /* actual map of first part */
469 map_addr = pci_map_resource(bar_addr, vfio_dev_fd,
475 /* if there's a second part, try to map it */
476 if (map_addr != MAP_FAILED
477 && memreg[1].offset && memreg[1].size) {
478 void *second_addr = RTE_PTR_ADD(bar_addr,
480 (uintptr_t)reg.offset);
481 map_addr = pci_map_resource(second_addr,
482 vfio_dev_fd, memreg[1].offset,
487 if (map_addr == MAP_FAILED || !map_addr) {
488 munmap(bar_addr, reg.size);
489 bar_addr = MAP_FAILED;
493 if (bar_addr == MAP_FAILED ||
494 (internal_config.process_type == RTE_PROC_SECONDARY &&
495 bar_addr != maps[i].addr)) {
496 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n", pci_addr, i,
499 if (internal_config.process_type == RTE_PROC_PRIMARY)
504 maps[i].addr = bar_addr;
505 maps[i].offset = reg.offset;
506 maps[i].size = reg.size;
507 maps[i].path = NULL; /* vfio doesn't have per-resource paths */
508 dev->mem_resource[i].addr = bar_addr;
511 /* if secondary process, do not set up interrupts */
512 if (internal_config.process_type == RTE_PROC_PRIMARY) {
513 if (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {
514 RTE_LOG(ERR, EAL, " %s error setting up interrupts!\n", pci_addr);
520 /* set bus mastering for the device */
521 if (pci_vfio_set_bus_master(vfio_dev_fd)) {
522 RTE_LOG(ERR, EAL, " %s cannot set up bus mastering!\n", pci_addr);
528 /* Reset the device */
529 ioctl(vfio_dev_fd, VFIO_DEVICE_RESET);
532 if (internal_config.process_type == RTE_PROC_PRIMARY)
533 TAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);
539 pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
540 struct rte_pci_ioport *p)
542 if (bar < VFIO_PCI_BAR0_REGION_INDEX ||
543 bar > VFIO_PCI_BAR5_REGION_INDEX) {
544 RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar);
549 p->base = VFIO_GET_REGION_ADDR(bar);
554 pci_vfio_ioport_read(struct rte_pci_ioport *p,
555 void *data, size_t len, off_t offset)
557 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
559 if (pread64(intr_handle->vfio_dev_fd, data,
560 len, p->base + offset) <= 0)
562 "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
563 VFIO_GET_REGION_IDX(p->base), (int)offset);
567 pci_vfio_ioport_write(struct rte_pci_ioport *p,
568 const void *data, size_t len, off_t offset)
570 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
572 if (pwrite64(intr_handle->vfio_dev_fd, data,
573 len, p->base + offset) <= 0)
575 "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
576 VFIO_GET_REGION_IDX(p->base), (int)offset);
580 pci_vfio_ioport_unmap(struct rte_pci_ioport *p)
587 pci_vfio_enable(void)
589 return vfio_enable("vfio_pci");
593 pci_vfio_is_enabled(void)
595 return vfio_is_enabled("vfio_pci");