2 *------------------------------------------------------------------
3 * Copyright (c) 2018 Cisco and/or its affiliates.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at:
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *------------------------------------------------------------------
21 #include <avf/virtchnl.h>
23 #include <vppinfra/types.h>
24 #include <vppinfra/error_bootstrap.h>
25 #include <vppinfra/lock.h>
28 #include <vlib/pci/pci.h>
30 #include <vnet/interface.h>
32 #define AVF_QUEUE_SZ_MAX 4096
33 #define AVF_QUEUE_SZ_MIN 64
35 #define AVF_AQ_ENQ_SUSPEND_TIME 50e-6
36 #define AVF_AQ_ENQ_MAX_WAIT_TIME 250e-3
38 #define AVF_RESET_SUSPEND_TIME 20e-3
39 #define AVF_RESET_MAX_WAIT_TIME 1
41 #define AVF_SEND_TO_PF_SUSPEND_TIME 10e-3
42 #define AVF_SEND_TO_PF_MAX_WAIT_TIME 1
44 #define AVF_RXD_STATUS(x) (1ULL << x)
45 #define AVF_RXD_STATUS_DD AVF_RXD_STATUS(0)
46 #define AVF_RXD_STATUS_EOP AVF_RXD_STATUS(1)
47 #define AVF_RXD_ERROR_SHIFT 19
48 #define AVF_RXD_PTYPE_SHIFT 30
49 #define AVF_RXD_LEN_SHIFT 38
50 #define AVF_RX_MAX_DESC_IN_CHAIN 5
52 #define AVF_RXD_ERROR_IPE (1ULL << (AVF_RXD_ERROR_SHIFT + 3))
53 #define AVF_RXD_ERROR_L4E (1ULL << (AVF_RXD_ERROR_SHIFT + 4))
55 #define AVF_TXD_CMD(x) (1 << (x + 4))
56 #define AVF_TXD_CMD_EXT(x, val) ((u64)val << (x + 4))
57 #define AVF_TXD_CMD_EOP AVF_TXD_CMD(0)
58 #define AVF_TXD_CMD_RS AVF_TXD_CMD(1)
59 #define AVF_TXD_CMD_RSV AVF_TXD_CMD(2)
61 #define AVF_TXD_CMD_IIPT_NONE AVF_TXD_CMD_EXT(5, 0)
62 #define AVF_TXD_CMD_IIPT_IPV6 AVF_TXD_CMD_EXT(5, 1)
63 #define AVF_TXD_CMD_IIPT_IPV4_NO_CSUM AVF_TXD_CMD_EXT(5, 2)
64 #define AVF_TXD_CMD_IIPT_IPV4 AVF_TXD_CMD_EXT(5, 3)
66 #define AVF_TXD_CMD_L4T_UNKNOWN AVF_TXD_CMD_EXT(8, 0)
67 #define AVF_TXD_CMD_L4T_TCP AVF_TXD_CMD_EXT(8, 1)
68 #define AVF_TXD_CMD_L4T_SCTP AVF_TXD_CMD_EXT(8, 2)
69 #define AVF_TXD_CMD_L4T_UDP AVF_TXD_CMD_EXT(8, 3)
71 #define AVF_TXD_OFFSET(x,factor,val) (((u64)val/(u64)factor) << (16 + x))
72 #define AVF_TXD_OFFSET_MACLEN(val) AVF_TXD_OFFSET( 0, 2, val)
73 #define AVF_TXD_OFFSET_IPLEN(val) AVF_TXD_OFFSET( 7, 4, val)
74 #define AVF_TXD_OFFSET_L4LEN(val) AVF_TXD_OFFSET(14, 4, val)
76 #define AVF_TXD_DTYP_CTX 0x1ULL
77 #define AVF_TXD_CTX_CMD_TSO AVF_TXD_CMD(0)
78 #define AVF_TXD_CTX_SEG(val,x) (((u64)val) << (30 + x))
79 #define AVF_TXD_CTX_SEG_TLEN(val) AVF_TXD_CTX_SEG(val,0)
80 #define AVF_TXD_CTX_SEG_MSS(val) AVF_TXD_CTX_SEG(val,20)
83 extern vlib_log_class_registration_t avf_log;
85 #define avf_log_err(dev, f, ...) \
86 vlib_log (VLIB_LOG_LEVEL_ERR, avf_log.class, "%U: " f, \
87 format_vlib_pci_addr, &dev->pci_addr, \
90 #define avf_log_warn(dev, f, ...) \
91 vlib_log (VLIB_LOG_LEVEL_WARNING, avf_log.class, "%U: " f, \
92 format_vlib_pci_addr, &dev->pci_addr, \
95 #define avf_log_debug(dev, f, ...) \
96 vlib_log (VLIB_LOG_LEVEL_DEBUG, avf_log.class, "%U: " f, \
97 format_vlib_pci_addr, &dev->pci_addr, \
100 #define foreach_avf_device_flags \
101 _(0, INITIALIZED, "initialized") \
102 _(1, ERROR, "error") \
103 _(2, ADMIN_UP, "admin-up") \
104 _(3, VA_DMA, "vaddr-dma") \
105 _(4, LINK_UP, "link-up") \
106 _(5, SHARED_TXQ_LOCK, "shared-txq-lock") \
108 _(7, PROMISC, "promisc") \
109 _(8, RX_INT, "rx-interrupts")
113 #define _(a, b, c) AVF_DEVICE_F_##b = (1 << a),
114 foreach_avf_device_flags
118 typedef volatile struct
127 u64 filter_status:32;
135 #ifdef CLIB_HAVE_VEC256
141 STATIC_ASSERT_SIZEOF (avf_rx_desc_t, 32);
143 typedef volatile struct
148 #ifdef CLIB_HAVE_VEC128
154 STATIC_ASSERT_SIZEOF (avf_tx_desc_t, 16);
158 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
159 volatile u32 *qrx_tail;
162 avf_rx_desc_t *descs;
166 u8 buffer_pool_index;
171 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
172 volatile u32 *qtx_tail;
175 u32 ctx_desc_placeholder_bi;
176 clib_spinlock_t lock;
177 avf_tx_desc_t *descs;
185 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
187 u32 per_interface_next_index;
192 vlib_pci_dev_handle_t pci_dev_handle;
212 virtchnl_pf_event_t *events;
223 virtchnl_link_speed_t link_speed;
224 vlib_pci_addr_t pci_addr;
227 virtchnl_eth_stats_t eth_stats;
228 virtchnl_eth_stats_t last_cleared_eth_stats;
234 #define AVF_RX_VECTOR_SZ VLIB_FRAME_SIZE
238 AVF_PROCESS_EVENT_START = 1,
239 AVF_PROCESS_EVENT_DELETE_IF = 2,
240 AVF_PROCESS_EVENT_AQ_INT = 3,
241 AVF_PROCESS_EVENT_REQ = 4,
242 } avf_process_event_t;
246 AVF_PROCESS_REQ_ADD_DEL_ETH_ADDR = 1,
247 AVF_PROCESS_REQ_CONFIG_PROMISC_MDDE = 2,
248 } avf_process_req_type_t;
252 avf_process_req_type_t type;
254 u32 calling_process_index;
256 int is_add, is_enable;
262 u64 qw1s[AVF_RX_MAX_DESC_IN_CHAIN - 1];
263 u32 buffers[AVF_RX_MAX_DESC_IN_CHAIN - 1];
268 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
269 vlib_buffer_t *bufs[AVF_RX_VECTOR_SZ];
270 u64 qw1s[AVF_RX_VECTOR_SZ];
271 avf_rx_tail_t tails[AVF_RX_VECTOR_SZ];
272 vlib_buffer_t buffer_template;
273 } avf_per_thread_data_t;
279 avf_device_t **devices;
280 avf_per_thread_data_t *per_thread_data;
283 extern avf_main_t avf_main;
287 vlib_pci_addr_t addr;
297 } avf_create_if_args_t;
299 void avf_create_if (vlib_main_t * vm, avf_create_if_args_t * args);
301 extern vlib_node_registration_t avf_input_node;
302 extern vlib_node_registration_t avf_process_node;
303 extern vnet_device_class_t avf_device_class;
306 format_function_t format_avf_device;
307 format_function_t format_avf_device_name;
308 format_function_t format_avf_input_trace;
310 static_always_inline avf_device_t *
311 avf_get_device (u32 dev_instance)
313 return pool_elt_at_index (avf_main.devices, dev_instance)[0];
317 avf_get_u32 (void *start, int offset)
319 return *(u32 *) (((u8 *) start) + offset);
323 avf_get_u64 (void *start, int offset)
325 return *(u64 *) (((u8 *) start) + offset);
329 avf_get_u32_bits (void *start, int offset, int first, int last)
331 u32 value = avf_get_u32 (start, offset);
332 if ((last == 0) && (first == 31))
335 value &= (1 << (first - last + 1)) - 1;
340 avf_get_u64_bits (void *start, int offset, int first, int last)
342 u64 value = avf_get_u64 (start, offset);
343 if ((last == 0) && (first == 63))
346 value &= (1 << (first - last + 1)) - 1;
351 avf_set_u32 (void *start, int offset, u32 value)
353 (*(u32 *) (((u8 *) start) + offset)) = value;
357 avf_reg_write (avf_device_t * ad, u32 addr, u32 val)
359 *(volatile u32 *) ((u8 *) ad->bar0 + addr) = val;
363 avf_reg_read (avf_device_t * ad, u32 addr)
365 return *(volatile u32 *) (ad->bar0 + addr);
369 avf_reg_flush (avf_device_t * ad)
371 avf_reg_read (ad, AVFGEN_RSTAT);
372 asm volatile ("":::"memory");
375 static_always_inline int
376 avf_rxd_is_not_eop (avf_rx_desc_t * d)
378 return (d->qword[1] & AVF_RXD_STATUS_EOP) == 0;
381 static_always_inline int
382 avf_rxd_is_not_dd (avf_rx_desc_t * d)
384 return (d->qword[1] & AVF_RXD_STATUS_DD) == 0;
392 u64 qw1s[AVF_RX_MAX_DESC_IN_CHAIN];
395 #define foreach_avf_tx_func_error \
396 _(SEGMENT_SIZE_EXCEEDED, "segment size exceeded") \
397 _(NO_FREE_SLOTS, "no free tx slots")
401 #define _(f,s) AVF_TX_ERROR_##f,
402 foreach_avf_tx_func_error
405 } avf_tx_func_error_t;
410 * fd.io coding-style-patch-verification: ON
413 * eval: (c-set-style "gnu")