src/plugins/dev_ena/ena_reg_defs.h

   1 /* SPDX-License-Identifier: Apache-2.0
   2  * Copyright(c) 2023 Cisco Systems, Inc.
   3  */
   4
   5 #ifndef _ENA_REG_DEFS_H_
   6 #define _ENA_REG_DEFS_H_
   7
   8 #include <vppinfra/clib.h>
   9 #include <vppinfra/error_bootstrap.h>
  10
  11 #define ena_reg_version_t_fields                                              \
  12   __ (8, minor)                                                               \
  13   __ (8, major)
  14
  15 #define ena_reg_controller_version_t_fields                                   \
  16   __ (8, subminor)                                                            \
  17   __ (8, minor)                                                               \
  18   __ (8, major)                                                               \
  19   __ (8, impl_id)
  20
  21 #define ena_reg_caps_t_fields                                                 \
  22   __ (1, contiguous_queue_required)                                           \
  23   __ (5, reset_timeout)                                                       \
  24   __ (2, _unused)                                                             \
  25   __ (8, dma_addr_width)                                                      \
  26   __ (4, admin_cmd_to)
  27
  28 #define ena_reg_aq_caps_t_fields                                              \
  29   __ (16, depth)                                                              \
  30   __ (16, entry_size)
  31
  32 #define ena_reg_acq_caps_t_fields                                             \
  33   __ (16, depth)                                                              \
  34   __ (16, entry_size)
  35
  36 #define ena_reg_aenq_caps_t_fields                                            \
  37   __ (16, depth)                                                              \
  38   __ (16, entry_size)
  39
  40 #define ena_reg_dev_ctl_t_fields                                              \
  41   __ (1, dev_reset)                                                           \
  42   __ (1, aq_restart)                                                          \
  43   __ (1, quiescent)                                                           \
  44   __ (1, io_resume)                                                           \
  45   __ (24, _unused)                                                            \
  46   __ (4, reset_reason)
  47
  48 #define ena_reg_dev_sts_t_fields                                              \
  49   __ (1, ready)                                                               \
  50   __ (1, aq_restart_in_progress)                                              \
  51   __ (1, aq_restart_finished)                                                 \
  52   __ (1, reset_in_progress)                                                   \
  53   __ (1, reset_finished)                                                      \
  54   __ (1, fatal_error)                                                         \
  55   __ (1, quiescent_state_in_progress)                                         \
  56   __ (1, quiescent_state_achieved)
  57
  58 #define ena_reg_mmio_reg_read_t_fields                                        \
  59   __ (16, req_id)                                                             \
  60   __ (16, reg_off)
  61
  62 #define ena_reg_rss_ind_entry_update_t_fields                                 \
  63   __ (16, index)                                                              \
  64   __ (16, cx_idx)
  65
  66 #define __(l, f) u32 f : l;
  67 #define _(n)                                                                  \
  68   typedef union                                                               \
  69   {                                                                           \
  70     struct                                                                    \
  71     {                                                                         \
  72       n##_fields;                                                             \
  73     };                                                                        \
  74     u32 as_u32;                                                               \
  75   } n;
  76
  77 _ (ena_reg_version_t)
  78 _ (ena_reg_controller_version_t)
  79 _ (ena_reg_caps_t)
  80 _ (ena_reg_aq_caps_t)
  81 _ (ena_reg_acq_caps_t)
  82 _ (ena_reg_aenq_caps_t)
  83 _ (ena_reg_dev_ctl_t)
  84 _ (ena_reg_dev_sts_t)
  85 _ (ena_reg_mmio_reg_read_t)
  86 _ (ena_reg_rss_ind_entry_update_t)
  87 #undef _
  88 #undef __
  89
  90 #define foreach_ena_reg                                                       \
  91   _ (0x00, 1, VERSION, ena_reg_version_t_fields)                              \
  92   _ (0x04, 1, CONTROLLER_VERSION, ena_reg_controller_version_t_fields)        \
  93   _ (0x08, 1, CAPS, ena_reg_caps_t_fields)                                    \
  94   _ (0x0c, 1, EXT_CAPS, )                                                     \
  95   _ (0x10, 1, AQ_BASE_LO, )                                                   \
  96   _ (0x14, 1, AQ_BASE_HI, )                                                   \
  97   _ (0x18, 1, AQ_CAPS, ena_reg_aq_caps_t_fields)                              \
  98   _ (0x20, 1, ACQ_BASE_LO, )                                                  \
  99   _ (0x24, 1, ACQ_BASE_HI, )                                                  \
 100   _ (0x28, 1, ACQ_CAPS, ena_reg_acq_caps_t_fields)                            \
 101   _ (0x2c, 0, AQ_DB, )                                                        \
 102   _ (0x30, 0, ACQ_TAIL, )                                                     \
 103   _ (0x34, 1, AENQ_CAPS, ena_reg_aenq_caps_t_fields)                          \
 104   _ (0x38, 0, AENQ_BASE_LO, )                                                 \
 105   _ (0x3c, 0, AENQ_BASE_HI, )                                                 \
 106   _ (0x40, 0, AENQ_HEAD_DB, )                                                 \
 107   _ (0x44, 0, AENQ_TAIL, )                                                    \
 108   _ (0x4c, 1, INTR_MASK, )                                                    \
 109   _ (0x54, 0, DEV_CTL, ena_reg_dev_ctl_t_fields)                              \
 110   _ (0x58, 1, DEV_STS, ena_reg_dev_sts_t_fields)                              \
 111   _ (0x5c, 0, MMIO_REG_READ, ena_reg_mmio_reg_read_t_fields)                  \
 112   _ (0x60, 0, MMIO_RESP_LO, )                                                 \
 113   _ (0x64, 0, MMIO_RESP_HI, )                                                 \
 114   _ (0x68, 0, RSS_IND_ENTRY_UPDATE, ena_reg_rss_ind_entry_update_t_fields)
 115
 116 typedef enum
 117 {
 118 #define _(o, r, n, f) ENA_REG_##n = o,
 119   foreach_ena_reg
 120 #undef _
 121 } ena_reg_t;
 122
 123 #define foreach_ena_reset_reason                                              \
 124   _ (0, NORMAL)                                                               \
 125   _ (1, KEEP_ALIVE_TO)                                                        \
 126   _ (2, ADMIN_TO)                                                             \
 127   _ (3, MISS_TX_CMPL)                                                         \
 128   _ (4, INV_RX_REQ_ID)                                                        \
 129   _ (5, INV_TX_REQ_ID)                                                        \
 130   _ (6, TOO_MANY_RX_DESCS)                                                    \
 131   _ (7, INIT_ERR)                                                             \
 132   _ (8, DRIVER_INVALID_STATE)                                                 \
 133   _ (9, OS_TRIGGER)                                                           \
 134   _ (10, OS_NETDEV_WD)                                                        \
 135   _ (11, SHUTDOWN)                                                            \
 136   _ (12, USER_TRIGGER)                                                        \
 137   _ (13, GENERIC)                                                             \
 138   _ (14, MISS_INTERRUPT)                                                      \
 139   _ (15, SUSPECTED_POLL_STARVATION)                                           \
 140   _ (16, RX_DESCRIPTOR_MALFORMED)                                             \
 141   _ (17, TX_DESCRIPTOR_MALFORMED)
 142
 143 typedef enum
 144 {
 145 #define _(o, n) ENA_RESET_REASON_##n = o,
 146   foreach_ena_reset_reason
 147 #undef _
 148 } ena_reset_reason_t;
 149
 150 #endif /* _ENA_REG_DEFS_H_ */