1 /* SPDX-License-Identifier: Apache-2.0
2 * Copyright(c) 2023 Cisco Systems, Inc.
6 #include <vnet/dev/dev.h>
8 #include <dev_ena/ena.h>
9 #include <dev_ena/ena_inlines.h>
11 VLIB_REGISTER_LOG_CLASS (ena_log, static) = {
13 .subclass_name = "reg",
17 ena_err (vnet_dev_t *dev, vnet_dev_rv_t rv, char *fmt, ...)
23 s = va_format (0, fmt, &va);
25 log_err (dev, "%v", s);
31 format_ena_reg_name (u8 *s, va_list *args)
33 int offset = va_arg (*args, int);
36 #define _(o, r, rn, m) [(o) >> 2] = #rn,
43 if (offset < 0 || offset >= ARRAY_LEN (reg_names) || reg_names[offset] == 0)
44 return format (s, "(unknown)");
45 return format (s, "%s", reg_names[offset]);
49 ena_reg_write (vnet_dev_t *dev, ena_reg_t reg, void *v)
51 ena_device_t *ed = vnet_dev_get_data (dev);
52 u32 *p = (u32 *) ((u8 *) ed->reg_bar + reg);
54 log_debug (dev, "%s: reg %U (0x%02x) value 0x%08x", __func__,
55 format_ena_reg_name, reg, reg, val);
56 __atomic_store_n (p, val, __ATOMIC_RELEASE);
60 ena_reg_set_dma_addr (vlib_main_t *vm, vnet_dev_t *dev, u32 rlo, u32 rhi,
63 uword pa = vnet_dev_get_dma_addr (vm, dev, p);
65 ena_reg_write (dev, rlo, ®);
67 ena_reg_write (dev, rhi, ®);
71 ena_reg_read (vnet_dev_t *dev, ena_reg_t reg, const void *v)
73 ena_device_t *ed = vnet_dev_get_data (dev);
74 vlib_main_t *vm = vlib_get_main ();
78 if (ed->readless == 0)
81 __atomic_load_n ((u32 *) ((u8 *) ed->reg_bar + reg), __ATOMIC_SEQ_CST);
85 u32 *p = (u32 *) ((u8 *) ed->reg_bar + ENA_REG_MMIO_REG_READ);
87 ena_reg_mmio_reg_read_t rr = { .reg_off = reg, .req_id = 1 };
88 ed->mmio_resp->req_id = 0;
89 ed->mmio_resp->reg_val = ~0;
91 __atomic_store_n (p, rr.as_u32, __ATOMIC_RELEASE);
93 t0 = vlib_time_now (vm);
94 while (ed->mmio_resp->req_id == 0 && dt < 0.2)
97 dt = vlib_time_now (vm) - t0;
100 rv = ed->mmio_resp->reg_val;
103 log_debug (dev, "%s: reg %U (0x%02x) value 0x%08x dt %.3fs", __func__,
104 format_ena_reg_name, reg, reg, rv, dt);
109 ena_reg_reset (vlib_main_t *vm, vnet_dev_t *dev, ena_reset_reason_t reason)
111 ena_device_t *ed = vnet_dev_get_data (dev);
112 ena_reg_version_t ver;
113 ena_reg_controller_version_t ctrl_ver;
114 ena_reg_caps_t caps = {};
115 ena_reg_dev_sts_t dev_sts = {};
116 ena_reg_dev_ctl_t reset_start = { .dev_reset = 1, .reset_reason = reason };
119 ena_reg_set_dma_addr (vm, dev, ENA_REG_MMIO_RESP_LO, ENA_REG_MMIO_RESP_HI,
122 ena_reg_read (dev, ENA_REG_DEV_STS, &dev_sts);
123 ena_reg_read (dev, ENA_REG_CAPS, &caps);
125 if (caps.as_u32 == ~0 && dev_sts.as_u32 == ~0)
126 return ena_err (dev, VNET_DEV_ERR_BUS, "failed to read regs");
128 if (dev_sts.ready == 0)
129 return VNET_DEV_ERR_NOT_READY;
131 log_debug (dev, "reg_reset: reset timeout is %u", caps.reset_timeout);
133 ena_reg_write (dev, ENA_REG_DEV_CTL, &reset_start);
136 ena_reg_set_dma_addr (vm, dev, ENA_REG_MMIO_RESP_LO, ENA_REG_MMIO_RESP_HI,
142 ena_reg_read (dev, ENA_REG_DEV_STS, &dev_sts);
143 if (dev_sts.reset_in_progress)
146 return ena_err (dev, VNET_DEV_ERR_BUS, "failed to initiate reset");
147 vlib_process_suspend (vm, 0.001);
150 ena_reg_write (dev, ENA_REG_DEV_CTL, &(ena_reg_dev_ctl_t){});
156 ena_reg_read (dev, ENA_REG_DEV_STS, &dev_sts);
157 if (dev_sts.reset_in_progress == 0)
160 return ena_err (dev, VNET_DEV_ERR_BUS, "failed to complete reset");
161 vlib_process_suspend (vm, 0.001);
164 ena_reg_read (dev, ENA_REG_VERSION, &ver);
165 ena_reg_read (dev, ENA_REG_CONTROLLER_VERSION, &ctrl_ver);
167 log_info (dev, "version %u.%u controller_version %u.%u.%u impl_id %u\n",
168 ver.major, ver.minor, ctrl_ver.major, ctrl_ver.minor,
169 ctrl_ver.subminor, ctrl_ver.impl_id);