1 /* SPDX-License-Identifier: Apache-2.0
2 * Copyright (c) 2023 Cisco Systems, Inc.
8 #include <vppinfra/clib.h>
9 #include <vppinfra/error_bootstrap.h>
10 #include <vppinfra/format.h>
11 #include <vnet/vnet.h>
12 #include <vnet/dev/dev.h>
14 #define iavf_reg_ctrl_t_fields \
17 __ (1, gio_master_disable) \
30 __ (1, port_sw_reset) \
31 __ (1, rx_flow_ctl_en) \
32 __ (1, tx_flow_ctl_en) \
33 __ (1, device_reset) \
34 __ (1, vlan_mode_enable) \
37 #define iavf_reg_status_t_fields \
45 __ (1, phy_reset_asserted) \
47 __ (1, gio_master_en_sts) \
55 #define iavf_reg_ctrl_ext_t_fields \
66 __ (1, eeprom_block_rst) \
68 __ (1, no_snoop_dis) \
69 __ (1, relaxed_ordering_dis) \
71 __ (1, phy_power_down_ena) \
72 __ (5, _reserved121) \
73 __ (1, ext_vlan_ena) \
74 __ (1, _reserved127) \
75 __ (1, driver_loaded) \
78 #define iavf_reg_mdic_t_fields \
88 #define iavf_reg_rctl_t_fields \
91 __ (1, store_bad_packets) \
92 __ (1, uc_promisc_ena) \
93 __ (1, mc_promisc_ena) \
94 __ (1, long_pkt_reception_ena) \
95 __ (2, loopback_mode) \
98 __ (2, mc_uc_tbl_off) \
100 __ (1, bcast_accept_mode) \
102 __ (1, vlan_filter_ena) \
103 __ (1, cannonical_form_ind_ena) \
104 __ (1, cannonical_form_ind_bit_val) \
105 __ (1, pad_small_rx_pkts) \
106 __ (1, discard_pause_frames) \
107 __ (1, pass_mac_ctrl_frames) \
108 __ (2, _reserved24) \
109 __ (1, strip_eth_crc) \
112 #define iavf_reg_tctl_t_fields \
116 __ (1, pad_short_pkts) \
117 __ (8, collision_threshold) \
118 __ (10, backoff_slot_time) \
120 __ (1, _reserved23) \
121 __ (1, retransmit_on_late_colision) \
124 #define iavf_reg_phpm_t_fields \
126 __ (1, restart_autoneg) \
128 __ (1, dis_1000_in_non_d0a) \
129 __ (1, link_energy_detect) \
130 __ (1, go_link_disc) \
131 __ (1, disable_1000) \
134 __ (1, dis_100_in_non_d0a) \
136 __ (1, disable_2500) \
137 __ (1, dis_2500_in_non_d0a) \
140 __ (1, link_enery_en) \
142 __ (1, dev_off_state) \
146 #define iavf_reg_manc_t_fields \
147 __ (1, flow_ctrl_discard) \
148 __ (1, ncsi_discard) \
149 __ (12, _reserved2) \
151 __ (1, tco_isolate) \
154 __ (1, keep_phy_link_up) \
156 __ (1, inhibit_ulp) \
157 __ (2, _reserved21) \
158 __ (1, en_xsum_filter) \
159 __ (1, en_ipv4_filter) \
160 __ (1, fixed_net_type) \
162 __ (1, ipv6_adv_only) \
168 #define iavf_reg_swsm_t_fields \
173 #define iavf_reg_fwsm_t_fields \
174 __ (1, eep_fw_semaphore) \
177 __ (1, eep_reload_ind) \
181 __ (6, ext_err_ind) \
182 __ (1, pcie_config_err_ind) \
183 __ (5, _reserved26) \
184 __ (1, factory_mac_addr_restored)
186 #define iavf_reg_sw_fw_sync_t_fields \
187 __ (1, sw_flash_sm) \
190 __ (1, sw_mac_csr_sm) \
196 __ (5, _reserved11) \
197 __ (1, fw_flash_sm) \
200 __ (1, fw_mac_csr_sm) \
201 __ (3, _reserved20) \
205 #define iavf_reg_srrctl_t_fields \
206 __ (7, bsizepacket) \
208 __ (6, bsizeheader) \
210 __ (1, _reserved16) \
215 __ (2, _reserved28) \
219 #define iavf_reg_rxdctl_t_fields \
223 __ (3, _reserved13) \
225 __ (4, _reserved21) \
230 #define iavf_reg_eec_t_fields \
232 __ (1, flash_in_use) \
236 __ (1, _reservedxi10) \
238 __ (4, pci_ana_done) \
239 __ (1, flash_detected) \
240 __ (2, _reserved20) \
241 __ (1, shadow_modified) \
243 __ (1, _reserved24) \
248 #define iavf_reg_eemngctl_t_fields \
255 __ (12, _reserved19) \
258 #define IAVF_REG_STRUCT(n) \
267 STATIC_ASSERT_SIZEOF (n, 4);
269 #define __(n, f) u32 f : n;
270 IAVF_REG_STRUCT (iavf_reg_status_t);
271 IAVF_REG_STRUCT (iavf_reg_ctrl_t);
272 IAVF_REG_STRUCT (iavf_reg_ctrl_ext_t);
273 IAVF_REG_STRUCT (iavf_reg_mdic_t);
274 IAVF_REG_STRUCT (iavf_reg_rctl_t);
275 IAVF_REG_STRUCT (iavf_reg_tctl_t);
276 IAVF_REG_STRUCT (iavf_reg_phpm_t);
277 IAVF_REG_STRUCT (iavf_reg_manc_t);
278 IAVF_REG_STRUCT (iavf_reg_swsm_t);
279 IAVF_REG_STRUCT (iavf_reg_fwsm_t);
280 IAVF_REG_STRUCT (iavf_reg_sw_fw_sync_t);
281 IAVF_REG_STRUCT (iavf_reg_srrctl_t);
282 IAVF_REG_STRUCT (iavf_reg_rxdctl_t);
283 IAVF_REG_STRUCT (iavf_reg_eec_t);
284 IAVF_REG_STRUCT (iavf_reg_eemngctl_t);
287 #define foreach_iavf_reg \
288 _ (0x00000, CTRL, iavf_reg_ctrl_t_fields) \
289 _ (0x00008, STATUS, iavf_reg_status_t_fields) \
290 _ (0x00018, CTRL_EXT, iavf_reg_ctrl_ext_t_fields) \
291 _ (0x00020, MDIC, iavf_reg_mdic_t_fields) \
292 _ (0x00100, RCTL, iavf_reg_rctl_t_fields) \
293 _ (0x00400, TCTL, iavf_reg_tctl_t_fields) \
294 _ (0x00404, TCTL_EXT, ) \
295 _ (0x00e14, PHPM, iavf_reg_phpm_t_fields) \
298 _ (0x05400, RAL0, ) \
299 _ (0x05404, RAH0, ) \
300 _ (0x05820, MANC, iavf_reg_manc_t_fields) \
301 _ (0x05b50, SWSM, iavf_reg_swsm_t_fields) \
302 _ (0x05b54, FWSM, iavf_reg_fwsm_t_fields) \
303 _ (0x05b5c, SW_FW_SYNC, iavf_reg_sw_fw_sync_t_fields) \
304 _ (0x0c000, RDBAL0, ) \
305 _ (0x0c004, RDBAH0, ) \
306 _ (0x0c008, RDLEN0, ) \
307 _ (0x0c00c, SRRCTL0, iavf_reg_srrctl_t_fields) \
308 _ (0x0c010, RDH0, ) \
309 _ (0x0c018, RDT0, ) \
310 _ (0x0c028, RXDCTL0, iavf_reg_rxdctl_t_fields) \
311 _ (0x12010, EEC, iavf_reg_eec_t_fields) \
312 _ (0x12030, EEMNGCTL, iavf_reg_eemngctl_t_fields)
314 #define IAVF_REG_RDBAL(n) (IAVF_REG_RDBAL0 + (n) *0x40)
315 #define IAVF_REG_RDBAH(n) (IAVF_REG_RDBAH0 + (n) *0x40)
316 #define IAVF_REG_RDLEN(n) (IAVF_REG_RDLEN0 + (n) *0x40)
317 #define IAVF_REG_SRRCTL(n) (IAVF_REG_SRRCTL0 + (n) *0x40)
318 #define IAVF_REG_RDH(n) (IAVF_REG_RDH0 + (n) *0x40)
319 #define IAVF_REG_RDT(n) (IAVF_REG_RDT0 + (n) *0x40)
320 #define IAVF_REG_RXDCTL(n) (IAVF_REG_RXDCTL0 + (n) *0x40)
321 #define IAVF_REG_SRRCTL(n) (IAVF_REG_SRRCTL0 + (n) *0x40)
325 #define _(o, n, f) IAVF_REG_##n = (o),
340 u32 sw_itr_indx_ena : 1;
349 STATIC_ASSERT_SIZEOF (iavf_dyn_ctl, 4);
360 } iavf_vfint_icr0_ena1;
362 STATIC_ASSERT_SIZEOF (iavf_vfint_icr0_ena1, 4);
364 #endif /* _IIAVF_REGS_H_ */