src/plugins/idpf/virtchnl2_lan_desc.h

   1 /*
   2  *------------------------------------------------------------------
   3  * Copyright (c) 2023 Intel and/or its affiliates.
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at:
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  *------------------------------------------------------------------
  16  */
  17
  18 #ifndef _IDPF_VIRTCHNL_LAN_DESC_H_
  19 #define _IDPF_VIRTCHNL_LAN_DESC_H_
  20
  21 /* VIRTCHNL2_TX_DESC_IDS
  22  * Transmit descriptor ID flags
  23  */
  24 #define foreach_idpf_txdid                                                    \
  25   _ (0, DATA)                                                                 \
  26   _ (1, CTX)                                                                  \
  27   _ (2, REINJECT_CTX)                                                         \
  28   _ (3, FLEX_DATA)                                                            \
  29   _ (4, FLEX_CTX)                                                             \
  30   _ (5, FLEX_TSO_CTX)                                                         \
  31   _ (6, FLEX_TSYN_L2TAG1)                                                     \
  32   _ (7, FLEX_L2TAG1_L2TAG2)                                                   \
  33   _ (8, FLEX_TSO_L2TAG2_PARSTAG_CTX)                                          \
  34   _ (9, FLEX_HOSTSPLIT_SA_TSO_CTX)                                            \
  35   _ (10, FLEX_HOSTSPLIT_SA_CTX)                                               \
  36   _ (11, FLEX_L2TAG2_CTX)                                                     \
  37   _ (12, FLEX_FLOW_SCHED)                                                     \
  38   _ (13, FLEX_HOSTSPLIT_TSO_CTX)                                              \
  39   _ (14, FLEX_HOSTSPLIT_CTX)                                                  \
  40   _ (15, DESC_DONE)
  41
  42 typedef enum
  43 {
  44 #define _(a, b) VIRTCHNL2_TXDID_##b = (1 << a),
  45   foreach_idpf_txdid
  46 #undef _
  47 } idpf_txdid_t;
  48
  49 /* VIRTCHNL2_RX_DESC_IDS
  50  * Receive descriptor IDs (range from 0 to 63)
  51  */
  52 #define foreach_virtchnl2_rxdid                                               \
  53   _ (0, 0_16B_BASE)                                                           \
  54   _ (1, 1_32B_BASE)                                                           \
  55   _ (2, 2_FLEX_SPLITQ)                                                        \
  56   _ (2, 2_FLEX_SQ_NIC)                                                        \
  57   _ (3, 3_FLEX_SQ_SW)                                                         \
  58   _ (4, 4_FLEX_SQ_NIC_VEB)                                                    \
  59   _ (5, 5_FLEX_SQ_NIC_ACL)                                                    \
  60   _ (6, 6_FLEX_SQ_NIC_2)                                                      \
  61   _ (7, 7_HW_RSVD)                                                            \
  62   _ (16, 16_COMMS_GENERIC)                                                    \
  63   _ (17, 17_COMMS_AUX_VLAN)                                                   \
  64   _ (18, 18_COMMS_AUX_IPV4)                                                   \
  65   _ (19, 19_COMMS_AUX_IPV6)                                                   \
  66   _ (20, 20_COMMS_AUX_FLOW)                                                   \
  67   _ (21, 21_COMMS_AUX_TCP)
  68
  69 typedef enum
  70 {
  71 #define _(v, n) VIRTCHNL2_RXDID_##n = v,
  72   foreach_virtchnl2_rxdid
  73 #undef _
  74 } virtchnl2_rxdid_t;
  75
  76 /* VIRTCHNL2_RX_DESC_ID_BITMASKS
  77  * Receive descriptor ID bitmasks
  78  */
  79 #define VIRTCHNL2_RXDID_0_16B_BASE_M    BIT (VIRTCHNL2_RXDID_0_16B_BASE)
  80 #define VIRTCHNL2_RXDID_1_32B_BASE_M    BIT (VIRTCHNL2_RXDID_1_32B_BASE)
  81 #define VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M BIT (VIRTCHNL2_RXDID_2_FLEX_SPLITQ)
  82 #define VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M BIT (VIRTCHNL2_RXDID_2_FLEX_SQ_NIC)
  83 #define VIRTCHNL2_RXDID_3_FLEX_SQ_SW_M  BIT (VIRTCHNL2_RXDID_3_FLEX_SQ_SW)
  84 #define VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB_M                                   \
  85   BIT (VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB)
  86 #define VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL_M                                   \
  87   BIT (VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL)
  88 #define VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2_M BIT (VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2)
  89 #define VIRTCHNL2_RXDID_7_HW_RSVD_M       BIT (VIRTCHNL2_RXDID_7_HW_RSVD)
  90 /* 9 through 15 are reserved */
  91 #define VIRTCHNL2_RXDID_16_COMMS_GENERIC_M                                    \
  92   BIT (VIRTCHNL2_RXDID_16_COMMS_GENERIC)
  93 #define VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN_M                                   \
  94   BIT (VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN)
  95 #define VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4_M                                   \
  96   BIT (VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4)
  97 #define VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6_M                                   \
  98   BIT (VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6)
  99 #define VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW_M                                   \
 100   BIT (VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW)
 101 #define VIRTCHNL2_RXDID_21_COMMS_AUX_TCP_M                                    \
 102   BIT (VIRTCHNL2_RXDID_21_COMMS_AUX_TCP)
 103 /* 22 through 63 are reserved */
 104
 105 /* Rx */
 106 /* For splitq virtchnl2_rx_flex_desc_adv desc members */
 107 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S 0
 108 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M                                    \
 109   MAKEMASK (0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S)
 110 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S 0
 111 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M                                    \
 112   MAKEMASK (0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S)
 113 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S 10
 114 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M                                  \
 115   MAKEMASK (0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S)
 116 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S 12
 117 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M                                      \
 118   MAKEMASK (0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S)
 119 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S 0
 120 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M                                 \
 121   MAKEMASK (0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S)
 122 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S 14
 123 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M                                      \
 124   BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S)
 125 #define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S 15
 126 #define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M                                  \
 127   BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S)
 128 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S 0
 129 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M                                  \
 130   MAKEMASK (0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S)
 131 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S 10
 132 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M                                      \
 133   BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S)
 134 #define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S 11
 135 #define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_M                                      \
 136   BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S)
 137 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S 12
 138 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M                                     \
 139   BIT_ULL (VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S)
 140 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S 13
 141 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M                                      \
 142   MAKEMASK (0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M)
 143
 144 #define foreach_virtchnl2_rx_flex_desc_adv_status0_qw1                        \
 145   _ (0, DD_S)                                                                 \
 146   _ (1, EOF_S)                                                                \
 147   _ (2, HBO_S)                                                                \
 148   _ (3, L3L4P_S)                                                              \
 149   _ (4, XSUM_IPE_S)                                                           \
 150   _ (5, XSUM_L4E_S)                                                           \
 151   _ (6, XSUM_EIPE_S)                                                          \
 152   _ (7, XSUM_EUDPE_S)
 153
 154 typedef enum
 155 {
 156 #define _(v, n) VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_##n = v,
 157   foreach_virtchnl2_rx_flex_desc_adv_status0_qw1
 158 #undef _
 159 } virtchnl2_rx_flex_desc_adv_status0_qw1_t;
 160
 161 #define foreach_virtchnl2_rx_flex_desc_adv_status0_qw0                        \
 162   _ (0, LPBK_S)                                                               \
 163   _ (1, IPV6EXADD_S)                                                          \
 164   _ (2, RXE_S)                                                                \
 165   _ (3, CRCP_S)                                                               \
 166   _ (4, RSS_VALID_S)                                                          \
 167   _ (5, L2TAG1P_S)                                                            \
 168   _ (6, XTRMD0_VALID_S)                                                       \
 169   _ (7, XTRMD1_VALID_S)                                                       \
 170   _ (8, LAST)
 171
 172 typedef enum
 173 {
 174 #define _(v, n) VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_##n = v,
 175   foreach_virtchnl2_rx_flex_desc_adv_status0_qw0
 176 #undef _
 177 } virtchnl2_rx_flex_desc_adv_status0_qw0_t;
 178
 179 #define foreach_virtchnl2_rx_flex_desc_adv_status1                            \
 180   _ (0, RSVD_S)                                                               \
 181   _ (2, ATRAEFAIL_S)                                                          \
 182   _ (3, L2TAG2P_S)                                                            \
 183   _ (4, XTRMD2_VALID_S)                                                       \
 184   _ (5, XTRMD3_VALID_S)                                                       \
 185   _ (6, XTRMD4_VALID_S)                                                       \
 186   _ (7, XTRMD5_VALID_S)                                                       \
 187   _ (8, LAST)
 188
 189 typedef enum
 190 {
 191 #define _(v, n) VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_##n = v,
 192   foreach_virtchnl2_rx_flex_desc_adv_status1
 193 #undef _
 194 } virtchnl2_rx_flex_desc_adv_status1_t;
 195
 196 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_S 0
 197 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M                                        \
 198   MAKEMASK (0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */
 199
 200 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S 0
 201 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M                                      \
 202   MAKEMASK (0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */
 203
 204 #define foreach_virtchnl2_rx_flex_desc_status0                                \
 205   _ (0, DD_S)                                                                 \
 206   _ (1, EOF_S)                                                                \
 207   _ (2, HBO_S)                                                                \
 208   _ (3, L3L4P_S)                                                              \
 209   _ (4, XSUM_IPE_S)                                                           \
 210   _ (5, XSUM_L4E_S)                                                           \
 211   _ (6, XSUM_EIPE_S)                                                          \
 212   _ (7, XSUM_EUDPE_S)                                                         \
 213   _ (8, LPBK_S)                                                               \
 214   _ (9, IPV6EXADD_S)                                                          \
 215   _ (10, RXE_S)                                                               \
 216   _ (11, CRCP_S)                                                              \
 217   _ (12, RSS_VALID_S)                                                         \
 218   _ (13, L2TAG1P_S)                                                           \
 219   _ (14, XTRMD0_VALID_S)                                                      \
 220   _ (15, XTRMD1_VALID_S)                                                      \
 221   _ (16, LAST)
 222
 223 typedef enum
 224 {
 225 #define _(v, n) VIRTCHNL2_RX_FLEX_DESC_STATUS0_##n = v,
 226   foreach_virtchnl2_rx_flex_desc_status0
 227 #undef _
 228 } virtchnl2_rx_flex_desc_status0_t;
 229
 230 #define foreach_virtchnl2_rx_flex_desc_status1                                \
 231   _ (0, CPM_S)                                                                \
 232   _ (4, NAT_S)                                                                \
 233   _ (5, CRYPTO_S)                                                             \
 234   _ (11, L2TAG2P_S)                                                           \
 235   _ (12, XTRMD2_VALID_S)                                                      \
 236   _ (13, XTRMD3_VALID_S)                                                      \
 237   _ (14, XTRMD4_VALID_S)                                                      \
 238   _ (15, XTRMD5_VALID_S)                                                      \
 239   _ (16, LAST)
 240
 241 typedef enum
 242 {
 243 #define _(v, n) VIRTCHNL2_RX_FLEX_DESC_STATUS1_##n = v,
 244   foreach_virtchnl2_rx_flex_desc_status1
 245 #undef _
 246 } virtchnl2_rx_flex_desc_status1_t;
 247
 248 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S 63
 249 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_M                                  \
 250   BIT_ULL (VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S)
 251 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S 52
 252 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_M                                 \
 253   MAKEMASK (0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S)
 254 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S 38
 255 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M                                 \
 256   MAKEMASK (0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S)
 257 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S 30
 258 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M                                    \
 259   MAKEMASK (0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S)
 260 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S 19
 261 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M                                    \
 262   MAKEMASK (0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S)
 263 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S 0
 264 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M                                   \
 265   MAKEMASK (0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S)
 266
 267 #define foreach_virtchnl2_rx_base_desc_status                                 \
 268   _ (0, DD_S)                                                                 \
 269   _ (1, EOF_S)                                                                \
 270   _ (2, L2TAG1P_S)                                                            \
 271   _ (3, L3L4P_S)                                                              \
 272   _ (4, CRCP_S)                                                               \
 273   _ (5, RSVD_S)                                                               \
 274   _ (8, EXT_UDP_0_S)                                                          \
 275   _ (9, UMBCAST_S)                                                            \
 276   _ (11, FLM_S)                                                               \
 277   _ (12, FLTSTAT_S)                                                           \
 278   _ (14, LPBK_S)                                                              \
 279   _ (15, IPV6EXADD_S)                                                         \
 280   _ (16, RSVD1_S)                                                             \
 281   _ (18, INT_UDP_0_S)                                                         \
 282   _ (19, LAST)
 283
 284 typedef enum
 285 {
 286 #define _(v, n) VIRTCHNL2_RX_BASE_DESC_STATUS_##n = v,
 287   foreach_virtchnl2_rx_base_desc_status
 288 #undef _
 289 } virtchnl2_rx_base_desc_status_t;
 290
 291 #define VIRTCHNL2_RX_BASE_DESC_EXT_STATUS_L2TAG2P_S 0
 292
 293 #define foreach_virtchnl2_rx_base_desc_error                                  \
 294   _ (0, RXE_S)                                                                \
 295   _ (1, ATRAEFAIL_S)                                                          \
 296   _ (2, HBO_S)                                                                \
 297   _ (3, L3L4E_S)                                                              \
 298   _ (3, IPE_S)                                                                \
 299   _ (4, L4E_S)                                                                \
 300   _ (5, EIPE_S)                                                               \
 301   _ (6, OVERSIZE_S)                                                           \
 302   _ (7, PPRS_S)
 303
 304 typedef enum
 305 {
 306 #define _(v, n) VIRTCHNL2_RX_BASE_DESC_ERROR_##n = v,
 307   foreach_virtchnl2_rx_base_desc_error
 308 #undef _
 309 } virtchnl2_rx_base_desc_error_t;
 310
 311 #define foreach_virtchnl2_rx_base_desc_fltstat                                \
 312   _ (0, NO_DATA)                                                              \
 313   _ (1, FD_ID)                                                                \
 314   _ (2, RSV)                                                                  \
 315   _ (3, RSS_HASH)
 316
 317 typedef enum
 318 {
 319 #define _(v, n) VIRTCHNL2_RX_BASE_DESC_FLTSTAT_##n = v,
 320   foreach_virtchnl2_rx_base_desc_fltstat
 321 #undef _
 322 } virtchnl2_rx_base_desc_fltstat_t;
 323
 324 /* Receive Descriptors */
 325 /* splitq buf
 326  |                                       16|                   0|
 327  ----------------------------------------------------------------
 328  | RSV                                     | Buffer ID          |
 329  ----------------------------------------------------------------
 330  | Rx packet buffer adresss                                     |
 331  ----------------------------------------------------------------
 332  | Rx header buffer adresss                                     |
 333  ----------------------------------------------------------------
 334  | RSV                                                          |
 335  ----------------------------------------------------------------
 336  |                                                             0|
 337  */
 338 typedef struct
 339 {
 340   struct
 341   {
 342     u16 buf_id;
 343     u16 rsvd0;
 344     u32 rsvd1;
 345   } qword0;
 346   u64 pkt_addr;
 347   u64 hdr_addr;
 348   u64 rsvd2;
 349 } virtchnl2_splitq_rx_buf_desc_t;
 350
 351 typedef struct
 352 {
 353   u64 pkt_addr;
 354   u64 hdr_addr;
 355   u64 rsvd1;
 356   u64 rsvd2;
 357 } virtchnl2_singleq_rx_buf_desc_t;
 358
 359 union virtchnl2_rx_buf_desc
 360 {
 361   virtchnl2_singleq_rx_buf_desc_t read;
 362   virtchnl2_splitq_rx_buf_desc_t split_rd;
 363 };
 364
 365 typedef struct
 366 {
 367   struct
 368   {
 369     struct
 370     {
 371       u16 mirroring_status;
 372       u16 l2tag1;
 373     } lo_dword;
 374     union
 375     {
 376       u32 rss;
 377       u32 fd_id;
 378     } hi_dword;
 379   } qword0;
 380   struct
 381   {
 382     u64 status_error_ptype_len;
 383   } qword1;
 384   struct
 385   {
 386     u16 ext_status;
 387     u16 rsvd;
 388     u16 l2tag2_1;
 389     u16 l2tag2_2;
 390   } qword2;
 391   struct
 392   {
 393     u32 reserved;
 394     u32 fd_id;
 395   } qword3;
 396 } virtchnl2_singleq_base_rx_desc_t;
 397
 398 typedef struct
 399 {
 400   /* Qword 0 */
 401   u8 rxdid;
 402   u8 mir_id_umb_cast;
 403   u16 ptype_flex_flags0;
 404   u16 pkt_len;
 405   u16 hdr_len_sph_flex_flags1;
 406
 407   /* Qword 1 */
 408   u16 status_error0;
 409   u16 l2tag1;
 410   u16 flex_meta0;
 411   u16 flex_meta1;
 412
 413   /* Qword 2 */
 414   u16 status_error1;
 415   u8 flex_flags2;
 416   u8 time_stamp_low;
 417   u16 l2tag2_1st;
 418   u16 l2tag2_2nd;
 419
 420   /* Qword 3 */
 421   u16 flex_meta2;
 422   u16 flex_meta3;
 423   union
 424   {
 425     struct
 426     {
 427       u16 flex_meta4;
 428       u16 flex_meta5;
 429     } flex;
 430     u32 ts_high;
 431   } flex_ts;
 432 } virtchnl2_rx_flex_desc_t;
 433
 434 typedef struct
 435 {
 436   /* Qword 0 */
 437   u8 rxdid;
 438   u8 mir_id_umb_cast;
 439   u16 ptype_flex_flags0;
 440   u16 pkt_len;
 441   u16 hdr_len_sph_flex_flags1;
 442
 443   /* Qword 1 */
 444   u16 status_error0;
 445   u16 l2tag1;
 446   u32 rss_hash;
 447
 448   /* Qword 2 */
 449   u16 status_error1;
 450   u8 flexi_flags2;
 451   u8 ts_low;
 452   u16 l2tag2_1st;
 453   u16 l2tag2_2nd;
 454
 455   /* Qword 3 */
 456   u32 flow_id;
 457   union
 458   {
 459     struct
 460     {
 461       u16 rsvd;
 462       u16 flow_id_ipv6;
 463     } flex;
 464     u32 ts_high;
 465   } flex_ts;
 466 } virtchnl2_rx_flex_desc_nic_t;
 467
 468 typedef struct
 469 {
 470   /* Qword 0 */
 471   u8 rxdid;
 472   u8 mir_id_umb_cast;
 473   u16 ptype_flex_flags0;
 474   u16 pkt_len;
 475   u16 hdr_len_sph_flex_flags1;
 476
 477   /* Qword 1 */
 478   u16 status_error0;
 479   u16 l2tag1;
 480   u16 src_vsi;
 481   u16 flex_md1_rsvd;
 482
 483   /* Qword 2 */
 484   u16 status_error1;
 485   u8 flex_flags2;
 486   u8 ts_low;
 487   u16 l2tag2_1st;
 488   u16 l2tag2_2nd;
 489
 490   /* Qword 3 */
 491   u32 rsvd;
 492   u32 ts_high;
 493 } virtchnl2_rx_flex_desc_sw_t;
 494
 495 typedef struct
 496 {
 497   /* Qword 0 */
 498   u8 rxdid;
 499   u8 mir_id_umb_cast;
 500   u16 ptype_flex_flags0;
 501   u16 pkt_len;
 502   u16 hdr_len_sph_flex_flags1;
 503
 504   /* Qword 1 */
 505   u16 status_error0;
 506   u16 l2tag1;
 507   u32 rss_hash;
 508
 509   /* Qword 2 */
 510   u16 status_error1;
 511   u8 flexi_flags2;
 512   u8 ts_low;
 513   u16 l2tag2_1st;
 514   u16 l2tag2_2nd;
 515
 516   /* Qword 3 */
 517   u16 flow_id;
 518   u16 src_vsi;
 519   union
 520   {
 521     struct
 522     {
 523       u16 rsvd;
 524       u16 flow_id_ipv6;
 525     } flex;
 526     u32 ts_high;
 527   } flex_ts;
 528 } virtchnl2_rx_flex_desc_nic_2_t;
 529
 530 typedef struct
 531 {
 532   /* Qword 0 */
 533   u8 rxdid_ucast;
 534   u8 status_err0_qw0;
 535   u16 ptype_err_fflags0;
 536   u16 pktlen_gen_bufq_id;
 537   u16 hdrlen_flags;
 538
 539   /* Qword 1 */
 540   u8 status_err0_qw1;
 541   u8 status_err1;
 542   u8 fflags1;
 543   u8 ts_low;
 544   u16 fmd0;
 545   u16 fmd1;
 546   /* Qword 2 */
 547   u16 fmd2;
 548   u8 fflags2;
 549   u8 hash3;
 550   u16 fmd3;
 551   u16 fmd4;
 552   /* Qword 3 */
 553   u16 fmd5;
 554   u16 fmd6;
 555   u16 fmd7_0;
 556   u16 fmd7_1;
 557 } virtchnl2_rx_flex_desc_adv_t;
 558
 559 typedef struct
 560 {
 561   /* Qword 0 */
 562   u8 rxdid_ucast;
 563   u8 status_err0_qw0;
 564   u16 ptype_err_fflags0;
 565   u16 pktlen_gen_bufq_id;
 566   u16 hdrlen_flags;
 567
 568   /* Qword 1 */
 569   u8 status_err0_qw1;
 570   u8 status_err1;
 571   u8 fflags1;
 572   u8 ts_low;
 573   u16 buf_id;
 574   union
 575   {
 576     u16 raw_cs;
 577     u16 l2tag1;
 578     u16 rscseglen;
 579   } misc;
 580   /* Qword 2 */
 581   u16 hash1;
 582   union
 583   {
 584     u8 fflags2;
 585     u8 mirrorid;
 586     u8 hash2;
 587   } ff2_mirrid_hash2;
 588   u8 hash3;
 589   u16 l2tag2;
 590   u16 fmd4;
 591   /* Qword 3 */
 592   u16 l2tag1;
 593   u16 fmd6;
 594   u32 ts_high;
 595 } virtchnl2_rx_flex_desc_adv_nic_3_t;
 596
 597 typedef union
 598 {
 599   virtchnl2_singleq_rx_buf_desc_t read;
 600   virtchnl2_singleq_base_rx_desc_t base_wb;
 601   virtchnl2_rx_flex_desc_t flex_wb;
 602   virtchnl2_rx_flex_desc_nic_t flex_nic_wb;
 603   virtchnl2_rx_flex_desc_sw_t flex_sw_wb;
 604   virtchnl2_rx_flex_desc_nic_2_t flex_nic_2_wb;
 605   virtchnl2_rx_flex_desc_adv_t flex_adv_wb;
 606   virtchnl2_rx_flex_desc_adv_nic_3_t flex_adv_nic_3_wb;
 607   u64 qword[4];
 608 } virtchnl2_rx_desc_t;
 609
 610 #endif /* _IDPF_VIRTCHNL_LAN_DESC_H_ */