2 * Copyright (c) 2016 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #ifndef included_ixge_h
17 #define included_ixge_h
19 #include <vnet/vnet.h>
20 #include <vlib/pci/pci.h>
22 #include <vnet/ethernet/sfp.h>
23 #include <vnet/ip/ip4_packet.h>
24 #include <vnet/ip/ip6_packet.h>
26 typedef volatile struct
28 /* [31:7] 128 byte aligned. */
29 u32 descriptor_address[2];
30 u32 n_descriptor_bytes;
32 /* [5] rx/tx descriptor dca enable
33 [6] rx packet head dca enable
34 [7] rx packet tail dca enable
35 [9] rx/tx descriptor relaxed order
36 [11] rx/tx descriptor write back relaxed order
37 [13] rx/tx data write/read relaxed order
38 [15] rx head data write relaxed order
39 [31:24] apic id for cpu's cache. */
44 /* [4:0] tail buffer size (in 1k byte units)
45 [13:8] head buffer size (in 64 byte units)
46 [24:22] lo free descriptors threshold (units of 64 descriptors)
47 [27:25] descriptor type 0 = legacy, 1 = advanced one buffer (e.g. tail),
48 2 = advanced header splitting (head + tail), 5 = advanced header
49 splitting (head only).
50 [28] drop if no descriptors available. */
54 CLIB_PAD_FROM_TO (0x1c, 0x28);
56 /* [7:0] rx/tx prefetch threshold
57 [15:8] rx/tx host threshold
58 [24:16] rx/tx write back threshold
60 [26] tx descriptor writeback flush
61 [30] rx strip vlan enable */
64 u32 rx_coallesce_control;
70 /* packets bytes lo hi */
80 /* [0] enables head write back. */
81 u32 head_index_write_back_address[2];
86 /* Only advanced descriptors are supported. */
91 } ixge_rx_to_hw_descriptor_t;
96 u16 n_packet_bytes_this_descriptor;
98 } ixge_rx_from_hw_descriptor_t;
100 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_LAYER2 (1 << (4 + 11))
101 /* Valid if not layer2. */
102 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4 (1 << (4 + 0))
103 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4_EXT (1 << (4 + 1))
104 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6 (1 << (4 + 2))
105 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6_EXT (1 << (4 + 3))
106 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_TCP (1 << (4 + 4))
107 #define IXGE_RX_DESCRIPTOR_STATUS0_IS_UDP (1 << (4 + 5))
108 #define IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET(s) (((s) >> 21) & 0x3ff)
110 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_OWNED_BY_SOFTWARE (1 << (0 + 0))
111 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET (1 << (0 + 1))
112 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_VLAN (1 << (0 + 3))
113 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED (1 << (0 + 4))
114 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED (1 << (0 + 5))
115 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED (1 << (0 + 6))
116 #define IXGE_RX_DESCRIPTOR_STATUS2_NOT_UNICAST (1 << (0 + 7))
117 #define IXGE_RX_DESCRIPTOR_STATUS2_IS_DOUBLE_VLAN (1 << (0 + 9))
118 #define IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR (1 << (0 + 10))
119 #define IXGE_RX_DESCRIPTOR_STATUS2_ETHERNET_ERROR (1 << (20 + 9))
120 #define IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR (1 << (20 + 10))
121 #define IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR (1 << (20 + 11))
123 /* For layer2 packets stats0 bottom 3 bits give ether type index from filter. */
124 #define IXGE_RX_DESCRIPTOR_STATUS0_LAYER2_ETHERNET_TYPE(s) ((s) & 7)
129 u16 n_bytes_this_buffer;
132 #define IXGE_TX_DESCRIPTOR_STATUS0_ADVANCED (3 << 4)
133 #define IXGE_TX_DESCRIPTOR_STATUS0_IS_ADVANCED (1 << (8 + 5))
134 #define IXGE_TX_DESCRIPTOR_STATUS0_LOG2_REPORT_STATUS (8 + 3)
135 #define IXGE_TX_DESCRIPTOR_STATUS0_REPORT_STATUS (1 << IXGE_TX_DESCRIPTOR_STATUS0_LOG2_REPORT_STATUS)
136 #define IXGE_TX_DESCRIPTOR_STATUS0_INSERT_FCS (1 << (8 + 1))
137 #define IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET (8 + 0)
138 #define IXGE_TX_DESCRIPTOR_STATUS0_IS_END_OF_PACKET (1 << IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET)
139 #define IXGE_TX_DESCRIPTOR_STATUS1_DONE (1 << 0)
140 #define IXGE_TX_DESCRIPTOR_STATUS1_CONTEXT(i) (/* valid */ (1 << 7) | ((i) << 4))
141 #define IXGE_TX_DESCRIPTOR_STATUS1_IPSEC_OFFLOAD (1 << (8 + 2))
142 #define IXGE_TX_DESCRIPTOR_STATUS1_INSERT_TCP_UDP_CHECKSUM (1 << (8 + 1))
143 #define IXGE_TX_DESCRIPTOR_STATUS1_INSERT_IP4_CHECKSUM (1 << (8 + 0))
144 #define IXGE_TX_DESCRIPTOR_STATUS0_N_BYTES_THIS_BUFFER(l) ((l) << 0)
145 #define IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET(l) ((l) << 14)
146 } ixge_tx_descriptor_t;
152 u8 checksum_start_offset;
153 u8 checksum_insert_offset;
154 u16 checksum_end_offset;
160 /* Byte offset after UDP/TCP header. */
163 u16 max_tcp_segment_size;
164 } __attribute__ ((packed)) ixge_tx_context_descriptor_t;
168 ixge_rx_to_hw_descriptor_t rx_to_hw;
169 ixge_rx_from_hw_descriptor_t rx_from_hw;
170 ixge_tx_descriptor_t tx;
174 typedef volatile struct
176 /* [2] pcie master disable
178 [26] global device reset */
181 /* [3:2] device id (0 or 1 for dual port chips)
185 [19] pcie master enable status */
186 u32 status_read_only;
187 CLIB_PAD_FROM_TO (0xc, 0x18);
188 /* [14] pf reset done
189 [17] relaxed ordering disable
190 [26] extended vlan enable
191 [28] driver loaded */
192 u32 extended_control;
193 CLIB_PAD_FROM_TO (0x1c, 0x20);
195 /* software definable pins.
198 sdp_is_native [23:16]
199 sdp_function [31:24].
202 CLIB_PAD_FROM_TO (0x24, 0x28);
209 CLIB_PAD_FROM_TO (0x2c, 0x4c);
212 CLIB_PAD_FROM_TO (0x50, 0x200);
216 CLIB_PAD_FROM_TO (0x204, 0x600);
218 CLIB_PAD_FROM_TO (0x604, 0x700);
222 u32 vflr_events_clear[4];
223 u32 mailbox_interrupt_status[4];
224 u32 mailbox_interrupt_enable[4];
225 CLIB_PAD_FROM_TO (0x730, 0x800);
230 u32 status_write_1_to_clear;
231 CLIB_PAD_FROM_TO (0x804, 0x808);
232 u32 status_write_1_to_set;
233 CLIB_PAD_FROM_TO (0x80c, 0x810);
234 u32 status_auto_clear_enable;
235 CLIB_PAD_FROM_TO (0x814, 0x820);
237 /* [11:3] minimum inter-interrupt interval
238 (2e-6 units; 20e-6 units for fast ethernet).
239 [15] low-latency interrupt moderation enable
240 [20:16] low-latency interrupt credit
241 [27:21] interval counter
242 [31] write disable for credit and counter (write only). */
245 u32 enable_write_1_to_set;
246 CLIB_PAD_FROM_TO (0x884, 0x888);
247 u32 enable_write_1_to_clear;
248 CLIB_PAD_FROM_TO (0x88c, 0x890);
249 u32 enable_auto_clear;
250 u32 msi_to_eitr_select;
251 /* [3:0] spd 0-3 interrupt detection enable
253 [5] other clear disable (makes other bits in status not clear on read)
256 CLIB_PAD_FROM_TO (0x89c, 0x900);
258 /* Defines interrupt mapping for 128 rx + 128 tx queues.
259 64 x 4 8 bit entries.
261 [5:0] bit in interrupt status for rx queue 2*i + 0
263 [13:8] bit for tx queue 2*i + 0
265 similar for rx 2*i + 1 and tx 2*i + 1. */
266 u32 queue_mapping[64];
268 /* tcp timer [7:0] and other interrupts [15:8] */
270 CLIB_PAD_FROM_TO (0xa04, 0xa90);
272 /* 64 interrupts determined by mappings. */
273 u32 status1_write_1_to_clear[4];
274 u32 enable1_write_1_to_set[4];
275 u32 enable1_write_1_to_clear[4];
276 CLIB_PAD_FROM_TO (0xac0, 0xad0);
277 u32 status1_enable_auto_clear[4];
278 CLIB_PAD_FROM_TO (0xae0, 0x1000);
281 ixge_dma_regs_t rx_dma0[64];
283 CLIB_PAD_FROM_TO (0x2000, 0x2140);
284 u32 dcb_rx_packet_plane_t4_config[8];
285 u32 dcb_rx_packet_plane_t4_status[8];
286 CLIB_PAD_FROM_TO (0x2180, 0x2300);
288 /* reg i defines mapping for 4 rx queues starting at 4*i + 0. */
289 u32 rx_queue_stats_mapping[32];
290 u32 rx_queue_stats_control;
292 CLIB_PAD_FROM_TO (0x2384, 0x2410);
293 u32 fc_user_descriptor_ptr[2];
294 u32 fc_buffer_control;
295 CLIB_PAD_FROM_TO (0x241c, 0x2420);
297 CLIB_PAD_FROM_TO (0x2424, 0x2430);
298 u32 dcb_packet_plane_control;
299 CLIB_PAD_FROM_TO (0x2434, 0x2f00);
302 u32 pf_queue_drop_enable;
303 CLIB_PAD_FROM_TO (0x2f08, 0x2f20);
304 u32 rx_dma_descriptor_cache_config;
305 CLIB_PAD_FROM_TO (0x2f24, 0x3000);
309 CLIB_PAD_FROM_TO (0x3004, 0x3008);
310 /* [15:0] ether type (little endian)
311 [31:16] opcode (big endian) */
312 u32 flow_control_control;
313 CLIB_PAD_FROM_TO (0x300c, 0x3020);
314 /* 3 bit traffic class for each of 8 priorities. */
315 u32 rx_priority_to_traffic_class;
316 CLIB_PAD_FROM_TO (0x3024, 0x3028);
317 u32 rx_coallesce_data_buffer_control;
318 CLIB_PAD_FROM_TO (0x302c, 0x3190);
319 u32 rx_packet_buffer_flush_detect;
320 CLIB_PAD_FROM_TO (0x3194, 0x3200);
321 u32 flow_control_tx_timers[4]; /* 2 timer values */
322 CLIB_PAD_FROM_TO (0x3210, 0x3220);
323 u32 flow_control_rx_threshold_lo[8];
324 CLIB_PAD_FROM_TO (0x3240, 0x3260);
325 u32 flow_control_rx_threshold_hi[8];
326 CLIB_PAD_FROM_TO (0x3280, 0x32a0);
327 u32 flow_control_refresh_threshold;
328 CLIB_PAD_FROM_TO (0x32a4, 0x3c00);
329 /* For each of 8 traffic classes (units of bytes). */
330 u32 rx_packet_buffer_size[8];
331 CLIB_PAD_FROM_TO (0x3c20, 0x3d00);
332 u32 flow_control_config;
333 CLIB_PAD_FROM_TO (0x3d04, 0x4200);
338 CLIB_PAD_FROM_TO (0x4204, 0x4208);
342 u32 auto_negotiation;
343 u32 link_partner_ability;
344 u32 auto_negotiation_tx_next_page;
345 u32 auto_negotiation_link_partner_next_page;
346 CLIB_PAD_FROM_TO (0x4228, 0x4240);
352 [2] enable frames up to max frame size register [31:16]
353 [10] pad frames < 64 bytes if specified by user
356 [17] turn off mdc between mdio packets */
359 /* [5] rx symbol error (all bits clear on read)
360 [6] rx illegal symbol
363 [9] rx remote fault */
366 u32 pause_and_pace_control;
367 CLIB_PAD_FROM_TO (0x424c, 0x425c);
370 CLIB_PAD_FROM_TO (0x4264, 0x4268);
372 /* [31:16] max frame size in bytes. */
373 u32 rx_max_frame_size;
374 CLIB_PAD_FROM_TO (0x426c, 0x4288);
377 [2] pcs receive link up? (latch lo)
380 [0] pcs 10g base r capable
381 [1] pcs 10g base x capable
382 [2] pcs 10g base w capable
385 [15:14] 2 => device present at this address (else not present) */
388 u32 base_x_pcs_status;
390 /* [0] pass unrecognized flow control frames
391 [1] discard pause frames
392 [2] rx priority flow control enable (only in dcb mode)
393 [3] rx flow control enable. */
396 /* [3:0] tx lanes change polarity
397 [7:4] rx lanes change polarity
398 [11:8] swizzle tx lanes
399 [15:12] swizzle rx lanes
400 4 x 2 bit tx lane swap
401 4 x 2 bit rx lane swap. */
407 [1] autoneg ack2 bit to transmit
408 [6:2] autoneg selector field to transmit
409 [8:7] 10g pma/pmd type 0 => xaui, 1 kx4, 2 cx4
410 [9] 1g pma/pmd type 0 => sfi, 1 => kx/bx
411 [10] disable 10g on without main power
412 [11] restart autoneg on transition to dx power state
416 1 => 10g kx4 parallel link no autoneg
427 u32 auto_negotiation_control;
429 /* [0] signal detect 1g/100m
430 [1] fec signal detect
431 [2] 10g serial pcs fec block lock
432 [3] 10g serial high error rate
433 [4] 10g serial pcs block lock
434 [5] kx/kx4/kr autoneg next page received
435 [6] kx/kx4/kr backplane autoneg next page received
436 [7] link status clear to read
437 [11:8] 10g signal detect (4 lanes) (for serial just lane 0)
438 [12] 10g serial signal detect
439 [16:13] 10g parallel lane sync status
440 [17] 10g parallel align status
442 [19] kx/kx4/kr backplane autoneg is idle
443 [20] 1g autoneg enabled
444 [21] 1g pcs enabled for sgmii
445 [22] 10g xgxs enabled
446 [23] 10g serial fec enabled (forward error detection)
447 [24] 10g kr pcs enabled
449 [27:26] mac link mode
459 [31] kx/kx4/kr backplane autoneg completed successfully. */
462 /* [17:16] pma/pmd for 10g serial
464 [18] disable dme pages */
465 u32 auto_negotiation_control2;
467 CLIB_PAD_FROM_TO (0x42ac, 0x42b0);
468 u32 link_partner_ability[2];
469 CLIB_PAD_FROM_TO (0x42b8, 0x42d0);
470 u32 manageability_control;
471 u32 link_partner_next_page[2];
472 CLIB_PAD_FROM_TO (0x42dc, 0x42e0);
476 CLIB_PAD_FROM_TO (0x42f0, 0x4314);
478 CLIB_PAD_FROM_TO (0x4318, 0x4324);
480 CLIB_PAD_FROM_TO (0x4328, 0x4900);
484 u32 tx_dcb_descriptor_plane_queue_select;
485 u32 tx_dcb_descriptor_plane_t1_config;
486 u32 tx_dcb_descriptor_plane_t1_status;
487 CLIB_PAD_FROM_TO (0x4910, 0x4950);
489 /* For each TC in units of 1k bytes. */
490 u32 tx_packet_buffer_thresholds[8];
491 CLIB_PAD_FROM_TO (0x4970, 0x4980);
498 } dcb_tx_rate_scheduler;
499 CLIB_PAD_FROM_TO (0x4990, 0x4a80);
501 CLIB_PAD_FROM_TO (0x4a84, 0x4a88);
502 u32 tx_dma_tcp_flags_control[2];
503 CLIB_PAD_FROM_TO (0x4a90, 0x4b00);
505 CLIB_PAD_FROM_TO (0x4c00, 0x5000);
508 u32 checksum_control;
509 CLIB_PAD_FROM_TO (0x5004, 0x5008);
510 u32 rx_filter_control;
511 CLIB_PAD_FROM_TO (0x500c, 0x5010);
512 u32 management_vlan_tag[8];
513 u32 management_udp_tcp_ports[8];
514 CLIB_PAD_FROM_TO (0x5050, 0x5078);
516 u32 extended_vlan_ether_type;
517 CLIB_PAD_FROM_TO (0x507c, 0x5080);
518 /* [1] store/dma bad packets
519 [8] accept all multicast
520 [9] accept all unicast
521 [10] accept all broadcast. */
523 CLIB_PAD_FROM_TO (0x5084, 0x5088);
524 /* [15:0] vlan ethernet type (0x8100) little endian
525 [28] cfi bit expected
526 [29] drop packets with unexpected cfi bit
527 [30] vlan filter enable. */
529 CLIB_PAD_FROM_TO (0x508c, 0x5090);
530 /* [1:0] hi bit of ethernet address for 12 bit index into multicast table
531 0 => 47, 1 => 46, 2 => 45, 3 => 43.
532 [2] enable multicast filter
534 u32 multicast_control;
535 CLIB_PAD_FROM_TO (0x5094, 0x5100);
537 CLIB_PAD_FROM_TO (0x5104, 0x5108);
539 CLIB_PAD_FROM_TO (0x510c, 0x5110);
540 u32 fc_filter_control;
541 CLIB_PAD_FROM_TO (0x5114, 0x5120);
542 u32 rx_message_type_lo;
543 CLIB_PAD_FROM_TO (0x5124, 0x5128);
544 /* [15:0] ethernet type (little endian)
545 [18:16] matche pri in vlan tag
546 [19] priority match enable
547 [25:20] virtualization pool
550 [30] ieee 1588 timestamp enable
552 (See ethernet_type_queue_select.) */
553 u32 ethernet_type_queue_filter[8];
554 CLIB_PAD_FROM_TO (0x5148, 0x5160);
555 /* [7:0] l2 ethernet type and
556 [15:8] l2 ethernet type or */
557 u32 management_decision_filters1[8];
558 u32 vf_vm_tx_switch_loopback_enable[2];
559 u32 rx_time_sync_control;
560 CLIB_PAD_FROM_TO (0x518c, 0x5190);
561 u32 management_ethernet_type_filters[4];
562 u32 rx_timestamp_attributes_lo;
564 u32 rx_timestamp_attributes_hi;
565 CLIB_PAD_FROM_TO (0x51ac, 0x51b0);
566 u32 pf_virtual_control;
567 CLIB_PAD_FROM_TO (0x51b4, 0x51d8);
568 u32 fc_offset_parameter;
569 CLIB_PAD_FROM_TO (0x51dc, 0x51e0);
572 CLIB_PAD_FROM_TO (0x51ec, 0x5200);
573 /* 12 bits determined by multicast_control
574 lookup bits in this vector. */
575 u32 multicast_enable[128];
577 /* [0] ethernet address [31:0]
578 [1] [15:0] ethernet address [47:32]
580 Index 0 is read from eeprom after reset. */
581 u32 rx_ethernet_address0[16][2];
583 CLIB_PAD_FROM_TO (0x5480, 0x5800);
585 CLIB_PAD_FROM_TO (0x5804, 0x5808);
586 u32 wake_up_filter_control;
587 CLIB_PAD_FROM_TO (0x580c, 0x5818);
588 u32 multiple_rx_queue_command_82598;
589 CLIB_PAD_FROM_TO (0x581c, 0x5820);
590 u32 management_control;
591 u32 management_filter_control;
592 CLIB_PAD_FROM_TO (0x5828, 0x5838);
593 u32 wake_up_ip4_address_valid;
594 CLIB_PAD_FROM_TO (0x583c, 0x5840);
595 u32 wake_up_ip4_address_table[4];
596 u32 management_control_to_host;
597 CLIB_PAD_FROM_TO (0x5854, 0x5880);
598 u32 wake_up_ip6_address_table[4];
600 /* unicast_and broadcast_and vlan_and ip_address_and
602 u32 management_decision_filters[8];
604 u32 management_ip4_or_ip6_address_filters[4][4];
605 CLIB_PAD_FROM_TO (0x58f0, 0x5900);
606 u32 wake_up_packet_length;
607 CLIB_PAD_FROM_TO (0x5904, 0x5910);
608 u32 management_ethernet_address_filters[4][2];
609 CLIB_PAD_FROM_TO (0x5930, 0x5a00);
610 u32 wake_up_packet_memory[32];
611 CLIB_PAD_FROM_TO (0x5a80, 0x5c00);
612 u32 redirection_table_82598[32];
613 u32 rss_random_keys_82598[10];
614 CLIB_PAD_FROM_TO (0x5ca8, 0x6000);
616 ixge_dma_regs_t tx_dma[128];
618 u32 pf_vm_vlan_insert[64];
619 u32 tx_dma_tcp_max_alloc_size_requests;
620 CLIB_PAD_FROM_TO (0x8104, 0x8110);
622 CLIB_PAD_FROM_TO (0x8118, 0x8120);
623 /* [0] dcb mode enable
624 [1] virtualization mode enable
625 [3:2] number of tcs/qs per pool. */
626 u32 multiple_tx_queues_command;
627 CLIB_PAD_FROM_TO (0x8124, 0x8200);
628 u32 pf_vf_anti_spoof[8];
629 u32 pf_dma_tx_switch_control;
630 CLIB_PAD_FROM_TO (0x8224, 0x82e0);
631 u32 tx_strict_low_latency_queues[4];
632 CLIB_PAD_FROM_TO (0x82f0, 0x8600);
633 u32 tx_queue_stats_mapping_82599[32];
634 u32 tx_queue_packet_counts[32];
635 u32 tx_queue_byte_counts[32][2];
641 u32 buffer_almost_full;
642 CLIB_PAD_FROM_TO (0x880c, 0x8810);
644 CLIB_PAD_FROM_TO (0x8814, 0x8900);
652 CLIB_PAD_FROM_TO (0x8918, 0x8a00);
663 /* untagged packets, encrypted packets, protected packets,
664 encrypted bytes, protected bytes */
666 CLIB_PAD_FROM_TO (0x8a50, 0x8c00);
672 u32 timestamp_value[2];
674 u32 increment_attributes;
675 u32 time_adjustment_offset[2];
677 u32 target_time[2][2];
678 CLIB_PAD_FROM_TO (0x8c34, 0x8c3c);
679 u32 aux_time_stamp[2][2];
680 CLIB_PAD_FROM_TO (0x8c4c, 0x8d00);
687 CLIB_PAD_FROM_TO (0x8d08, 0x8e00);
699 CLIB_PAD_FROM_TO (0x8e34, 0x8f00);
712 CLIB_PAD_FROM_TO (0x8f84, 0x9000);
715 /* 4 wake up, 2 management, 2 wake up. */
716 u32 flexible_filters[8][16][4];
717 CLIB_PAD_FROM_TO (0x9800, 0xa000);
720 u32 vlan_filter[128];
722 /* [0] ethernet address [31:0]
723 [1] [15:0] ethernet address [47:32]
725 Index 0 is read from eeprom after reset. */
726 u32 rx_ethernet_address1[128][2];
728 /* select one of 64 pools for each rx address. */
729 u32 rx_ethernet_address_pool_select[128][2];
730 CLIB_PAD_FROM_TO (0xaa00, 0xc800);
731 u32 tx_priority_to_traffic_class;
732 CLIB_PAD_FROM_TO (0xc804, 0xcc00);
734 /* In bytes units of 1k. Total packet buffer is 160k. */
735 u32 tx_packet_buffer_size[8];
737 CLIB_PAD_FROM_TO (0xcc20, 0xcd10);
738 u32 tx_manageability_tc_mapping;
739 CLIB_PAD_FROM_TO (0xcd14, 0xcd20);
740 u32 dcb_tx_packet_plane_t2_config[8];
741 u32 dcb_tx_packet_plane_t2_status[8];
742 CLIB_PAD_FROM_TO (0xcd60, 0xce00);
744 u32 tx_flow_control_status;
745 CLIB_PAD_FROM_TO (0xce04, 0xd000);
747 ixge_dma_regs_t rx_dma1[64];
751 /* Bigendian ip4 src/dst address. */
752 u32 src_address[128];
753 u32 dst_address[128];
755 /* TCP/UDP ports [15:0] src [31:16] dst; bigendian. */
756 u32 tcp_udp_port[128];
758 /* [1:0] protocol tcp, udp, sctp, other
759 [4:2] match priority (highest wins)
761 [25] src address match disable
762 [26] dst address match disable
763 [27] src port match disable
764 [28] dst port match disable
765 [29] protocol match disable
766 [30] pool match disable
772 [20] low-latency interrupt
777 CLIB_PAD_FROM_TO (0xea00, 0xeb00);
778 /* 4 bit rss output index indexed by 7 bit hash.
779 128 8 bit fields = 32 registers. */
780 u32 redirection_table_82599[32];
782 u32 rss_random_key_82599[10];
783 CLIB_PAD_FROM_TO (0xeba8, 0xec00);
785 [22:16] rx queue index
786 [29] low-latency interrupt on match
788 u32 ethernet_type_queue_select[8];
789 CLIB_PAD_FROM_TO (0xec20, 0xec30);
790 u32 syn_packet_queue_filter;
791 CLIB_PAD_FROM_TO (0xec34, 0xec60);
792 u32 immediate_interrupt_rx_vlan_priority;
793 CLIB_PAD_FROM_TO (0xec64, 0xec70);
794 u32 rss_queues_per_traffic_class;
795 CLIB_PAD_FROM_TO (0xec74, 0xec90);
796 u32 lli_size_threshold;
797 CLIB_PAD_FROM_TO (0xec94, 0xed00);
802 CLIB_PAD_FROM_TO (0xed04, 0xed10);
804 CLIB_PAD_FROM_TO (0xed30, 0xee00);
809 /* [1:0] packet buffer allocation 0 => disabled, else 64k*2^(f-1)
810 [3] packet buffer initialization done
811 [4] perfetch match mode
812 [5] report status in rss field of rx descriptors
813 [7] report status always
815 [20:16] flex 2 byte packet offset (units of 2 bytes)
816 [27:24] max linked list length
817 [31:28] full threshold. */
819 CLIB_PAD_FROM_TO (0xee04, 0xee0c);
823 /* [1:0] 0 => no action, 1 => add, 2 => remove, 3 => query.
824 [2] valid filter found by query command
825 [3] filter update override
827 [6:5] l4 protocol reserved, udp, tcp, sctp
830 [9] packet drop action
831 [10] matched packet generates low-latency interrupt
832 [11] last in linked list
839 CLIB_PAD_FROM_TO (0xee30, 0xee3c);
840 /* ip4 dst/src address, tcp ports, udp ports.
841 set bits mean bit is ignored. */
845 u32 failed_usage_stats;
846 u32 filters_match_stats;
847 u32 filters_miss_stats;
848 CLIB_PAD_FROM_TO (0xee60, 0xee68);
849 /* Lookup, signature. */
851 /* [15:0] ip6 src address 1 bit per byte
852 [31:16] ip6 dst address. */
861 CLIB_PAD_FROM_TO (0xee78, 0xf000);
867 u32 vlan_pool_filter[64];
868 u32 vlan_pool_filter_bitmap[128];
869 u32 dst_ethernet_address[128];
871 u32 mirror_rule_vlan[8];
872 u32 mirror_rule_pool[8];
873 CLIB_PAD_FROM_TO (0xf650, 0x10010);
876 u32 eeprom_flash_control;
880 [31:16] read data. */
882 CLIB_PAD_FROM_TO (0x10018, 0x1001c);
884 CLIB_PAD_FROM_TO (0x10020, 0x10114);
888 CLIB_PAD_FROM_TO (0x10120, 0x1013c);
890 u32 software_semaphore;
891 CLIB_PAD_FROM_TO (0x10144, 0x10148);
892 u32 firmware_semaphore;
893 CLIB_PAD_FROM_TO (0x1014c, 0x10160);
894 u32 software_firmware_sync;
895 CLIB_PAD_FROM_TO (0x10164, 0x10200);
896 u32 general_rx_control;
897 CLIB_PAD_FROM_TO (0x10204, 0x11000);
902 CLIB_PAD_FROM_TO (0x11004, 0x11010);
903 /* [3:0] enable counters
904 [7:4] leaky bucket counter mode
909 /* [7:0],[15:8],[23:16],[31:24] event for counters 0-3.
912 0x10 reqs that reached timeout
915 CLIB_PAD_FROM_TO (0x11018, 0x11020);
916 u32 counters_clear_on_read[4];
917 u32 counter_config[4];
923 CLIB_PAD_FROM_TO (0x11048, 0x11050);
924 u32 extended_control;
925 CLIB_PAD_FROM_TO (0x11054, 0x11064);
926 u32 mirrored_revision_id;
927 CLIB_PAD_FROM_TO (0x11068, 0x11070);
928 u32 dca_requester_id_information;
930 /* [0] global disable
931 [4:1] mode: 0 => legacy, 1 => dca 1.0. */
933 CLIB_PAD_FROM_TO (0x11078, 0x110b0);
934 /* [0] pci completion abort
935 [1] unsupported i/o address
936 [2] wrong byte enable
938 u32 pcie_interrupt_status;
939 CLIB_PAD_FROM_TO (0x110b4, 0x110b8);
940 u32 pcie_interrupt_enable;
941 CLIB_PAD_FROM_TO (0x110bc, 0x110c0);
942 u32 msi_x_pba_clear[8];
943 CLIB_PAD_FROM_TO (0x110e0, 0x12300);
946 u32 interrupt_throttle1[128 - 24];
947 CLIB_PAD_FROM_TO (0x124a0, 0x14f00);
949 u32 core_analog_config;
950 CLIB_PAD_FROM_TO (0x14f04, 0x14f10);
951 u32 core_common_config;
952 CLIB_PAD_FROM_TO (0x14f14, 0x15f14);
954 u32 link_sec_software_firmware_interface;
961 /* Addresses bigendian. */
966 ip6_address_t src_address;
972 ip4_address_t src_address, dst_address;
976 /* [15:0] src port (little endian).
980 /* [15:0] vlan (cfi bit set to 0).
981 [31:16] flex bytes. bigendian. */
982 u32 vlan_and_flex_word;
986 [31:16] signature (signature filers)/sw-index (perfect match). */
991 } ixge_flow_director_key_t;
994 ixge_throttle_queue_interrupt (ixge_regs_t * r,
995 u32 queue_interrupt_index,
996 f64 inter_interrupt_interval_in_secs)
999 (queue_interrupt_index < ARRAY_LEN (r->interrupt.throttle0)
1000 ? &r->interrupt.throttle0[queue_interrupt_index]
1001 : &r->interrupt_throttle1[queue_interrupt_index]);
1002 ASSERT (queue_interrupt_index < 128);
1004 i32 i, mask = (1 << 9) - 1;
1006 i = flt_round_nearest (inter_interrupt_interval_in_secs / 2e-6);
1008 i = i >= mask ? mask : i;
1016 #define foreach_ixge_counter \
1017 _ (0x40d0, rx_total_packets) \
1018 _64 (0x40c0, rx_total_bytes) \
1019 _ (0x41b0, rx_good_packets_before_filtering) \
1020 _64 (0x41b4, rx_good_bytes_before_filtering) \
1021 _ (0x2f50, rx_dma_good_packets) \
1022 _64 (0x2f54, rx_dma_good_bytes) \
1023 _ (0x2f5c, rx_dma_duplicated_good_packets) \
1024 _64 (0x2f60, rx_dma_duplicated_good_bytes) \
1025 _ (0x2f68, rx_dma_good_loopback_packets) \
1026 _64 (0x2f6c, rx_dma_good_loopback_bytes) \
1027 _ (0x2f74, rx_dma_good_duplicated_loopback_packets) \
1028 _64 (0x2f78, rx_dma_good_duplicated_loopback_bytes) \
1029 _ (0x4074, rx_good_packets) \
1030 _64 (0x4088, rx_good_bytes) \
1031 _ (0x407c, rx_multicast_packets) \
1032 _ (0x4078, rx_broadcast_packets) \
1033 _ (0x405c, rx_64_byte_packets) \
1034 _ (0x4060, rx_65_127_byte_packets) \
1035 _ (0x4064, rx_128_255_byte_packets) \
1036 _ (0x4068, rx_256_511_byte_packets) \
1037 _ (0x406c, rx_512_1023_byte_packets) \
1038 _ (0x4070, rx_gt_1023_byte_packets) \
1039 _ (0x4000, rx_crc_errors) \
1040 _ (0x4120, rx_ip_checksum_errors) \
1041 _ (0x4004, rx_illegal_symbol_errors) \
1042 _ (0x4008, rx_error_symbol_errors) \
1043 _ (0x4034, rx_mac_local_faults) \
1044 _ (0x4038, rx_mac_remote_faults) \
1045 _ (0x4040, rx_length_errors) \
1046 _ (0x41a4, rx_xons) \
1047 _ (0x41a8, rx_xoffs) \
1048 _ (0x40a4, rx_undersize_packets) \
1049 _ (0x40a8, rx_fragments) \
1050 _ (0x40ac, rx_oversize_packets) \
1051 _ (0x40b0, rx_jabbers) \
1052 _ (0x40b4, rx_management_packets) \
1053 _ (0x40b8, rx_management_drops) \
1054 _ (0x3fa0, rx_missed_packets_pool_0) \
1055 _ (0x40d4, tx_total_packets) \
1056 _ (0x4080, tx_good_packets) \
1057 _64 (0x4090, tx_good_bytes) \
1058 _ (0x40f0, tx_multicast_packets) \
1059 _ (0x40f4, tx_broadcast_packets) \
1060 _ (0x87a0, tx_dma_good_packets) \
1061 _64 (0x87a4, tx_dma_good_bytes) \
1062 _ (0x40d8, tx_64_byte_packets) \
1063 _ (0x40dc, tx_65_127_byte_packets) \
1064 _ (0x40e0, tx_128_255_byte_packets) \
1065 _ (0x40e4, tx_256_511_byte_packets) \
1066 _ (0x40e8, tx_512_1023_byte_packets) \
1067 _ (0x40ec, tx_gt_1023_byte_packets) \
1068 _ (0x4010, tx_undersize_drops) \
1069 _ (0x8780, switch_security_violation_packets) \
1070 _ (0x5118, fc_crc_errors) \
1071 _ (0x241c, fc_rx_drops) \
1072 _ (0x2424, fc_last_error_count) \
1073 _ (0x2428, fcoe_rx_packets) \
1074 _ (0x242c, fcoe_rx_dwords) \
1075 _ (0x8784, fcoe_tx_packets) \
1076 _ (0x8788, fcoe_tx_dwords) \
1077 _ (0x1030, queue_0_rx_count) \
1078 _ (0x1430, queue_0_drop_count) \
1079 _ (0x1070, queue_1_rx_count) \
1080 _ (0x1470, queue_1_drop_count) \
1081 _ (0x10b0, queue_2_rx_count) \
1082 _ (0x14b0, queue_2_drop_count) \
1083 _ (0x10f0, queue_3_rx_count) \
1084 _ (0x14f0, queue_3_drop_count) \
1085 _ (0x1130, queue_4_rx_count) \
1086 _ (0x1530, queue_4_drop_count) \
1087 _ (0x1170, queue_5_rx_count) \
1088 _ (0x1570, queue_5_drop_count) \
1089 _ (0x11b0, queue_6_rx_count) \
1090 _ (0x15b0, queue_6_drop_count) \
1091 _ (0x11f0, queue_7_rx_count) \
1092 _ (0x15f0, queue_7_drop_count) \
1093 _ (0x1230, queue_8_rx_count) \
1094 _ (0x1630, queue_8_drop_count) \
1095 _ (0x1270, queue_9_rx_count) \
1096 _ (0x1270, queue_9_drop_count)
1103 #define _(a,f) IXGE_COUNTER_##f,
1104 #define _64(a,f) _(a,f)
1105 foreach_ixge_counter
1109 } ixge_counter_type_t;
1115 /* 32 bit ID read from ID registers. */
1121 /* Cache aligned descriptors. */
1122 ixge_descriptor_t *descriptors;
1124 /* Number of descriptors in table. */
1127 /* Software head and tail pointers into descriptor ring. */
1128 u32 head_index, tail_index;
1130 /* Index into dma_queues vector. */
1133 /* Buffer indices corresponding to each active descriptor. */
1134 u32 *descriptor_buffer_indices;
1140 u32 *volatile head_index_write_back;
1142 u32 n_buffers_on_ring;
1147 /* Buffer indices to use to replenish each descriptor. */
1148 u32 *replenish_buffer_indices;
1150 vlib_node_runtime_t *node;
1153 u32 saved_start_of_packet_buffer_index;
1155 u32 saved_start_of_packet_next_index;
1156 u32 saved_last_buffer_index;
1158 u32 is_start_of_packet;
1160 u32 n_descriptors_done_total;
1162 u32 n_descriptors_done_this_call;
1169 #define foreach_ixge_pci_device_id \
1171 _ (82598_bx, 0x1508) \
1172 _ (82598af_dual_port, 0x10c6) \
1173 _ (82598af_single_port, 0x10c7) \
1174 _ (82598at, 0x10c8) \
1175 _ (82598at2, 0x150b) \
1176 _ (82598eb_sfp_lom, 0x10db) \
1177 _ (82598eb_cx4, 0x10dd) \
1178 _ (82598_cx4_dual_port, 0x10ec) \
1179 _ (82598_da_dual_port, 0x10f1) \
1180 _ (82598_sr_dual_port_em, 0x10e1) \
1181 _ (82598eb_xf_lr, 0x10f4) \
1182 _ (82599_kx4, 0x10f7) \
1183 _ (82599_kx4_mezz, 0x1514) \
1184 _ (82599_kr, 0x1517) \
1185 _ (82599_combo_backplane, 0x10f8) \
1186 _ (82599_cx4, 0x10f9) \
1187 _ (82599_sfp, 0x10fb) \
1188 _ (82599_backplane_fcoe, 0x152a) \
1189 _ (82599_sfp_fcoe, 0x1529) \
1190 _ (82599_sfp_em, 0x1507) \
1191 _ (82599_xaui_lom, 0x10fc) \
1192 _ (82599_t3_lom, 0x151c) \
1197 #define _(f,n) IXGE_##f = n,
1198 foreach_ixge_pci_device_id
1200 } ixge_pci_device_id_t;
1207 /* Specific next index when using dynamic redirection */
1208 u32 per_interface_next_index;
1211 vlib_pci_dev_handle_t pci_dev_handle;
1213 /* From PCI config space header. */
1214 ixge_pci_device_id_t device_id;
1221 /* VLIB interface for this instance. */
1222 u32 vlib_hw_if_index, vlib_sw_if_index;
1224 ixge_dma_queue_t *dma_queues[VLIB_N_RX_TX];
1226 /* Phy index (0 or 1) and address on MDI bus. */
1230 /* Value of link_status register at last link change. */
1231 u32 link_status_at_last_link_change;
1234 sfp_eeprom_t sfp_eeprom;
1237 u64 counters[IXGE_N_COUNTER], counters_last_clear[IXGE_N_COUNTER];
1242 vlib_main_t *vlib_main;
1244 /* Vector of devices. */
1245 ixge_device_t *devices;
1247 /* Descriptor ring sizes. */
1248 u32 n_descriptors[VLIB_N_RX_TX];
1250 /* RX buffer size. Must be at least 1k; will be rounded to
1251 next largest 1k size. */
1252 u32 n_bytes_in_rx_buffer;
1254 u32 n_descriptors_per_cache_line;
1256 u32 process_node_index;
1258 /* Template and mask for initializing/validating TX descriptors. */
1259 ixge_tx_descriptor_t tx_descriptor_template, tx_descriptor_template_mask;
1261 /* Vector of buffers for which TX is done and can be freed. */
1262 u32 *tx_buffers_pending_free;
1264 u32 *rx_buffers_to_add;
1266 f64 time_last_stats_update;
1268 vlib_physmem_region_index_t physmem_region;
1269 int physmem_region_allocated;
1272 extern ixge_main_t ixge_main;
1273 extern vnet_device_class_t ixge_device_class;
1277 IXGE_RX_NEXT_IP4_INPUT,
1278 IXGE_RX_NEXT_IP6_INPUT,
1279 IXGE_RX_NEXT_ETHERNET_INPUT,
1284 void ixge_set_next_node (ixge_rx_next_t, char *);
1286 #endif /* included_ixge_h */
1289 * fd.io coding-style-patch-verification: ON
1292 * eval: (c-set-style "gnu")