2 *------------------------------------------------------------------
3 * Copyright (c) 2018 Cisco and/or its affiliates.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at:
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *------------------------------------------------------------------
18 #define MVCONF_DBG_LEVEL 0
19 #define MVCONF_PP2_BPOOL_COOKIE_SIZE 32
20 #define MVCONF_PP2_BPOOL_DMA_ADDR_SIZE 64
21 #define MVCONF_DMA_PHYS_ADDR_T_SIZE 64
22 #define MVCONF_SYS_DMA_UIO
23 #define MVCONF_TYPES_PUBLIC
24 #define MVCONF_DMA_PHYS_ADDR_T_PUBLIC
26 #include <vlib/vlib.h>
29 #include "env/mv_sys_dma.h"
30 #include "drivers/mv_pp2.h"
31 #include <drivers/mv_pp2_bpool.h>
32 #include <drivers/mv_pp2_ppio.h>
36 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
38 struct pp2_bpool *bpool;
43 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
52 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
54 #define MRVL_PP2_IF_F_ADMIN_UP (1 << 0)
55 struct pp2_ppio *ppio;
56 u32 per_interface_next_index;
59 mrvl_pp2_outq_t *outqs;
66 #define MRVL_PP2_BUFF_BATCH_SZ VLIB_FRAME_SIZE
70 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
72 struct pp2_ppio_desc *descs;
73 struct buff_release_entry bre[MRVL_PP2_BUFF_BATCH_SZ];
74 u32 buffers[VLIB_FRAME_SIZE];
75 } mrvl_pp2_per_thread_data_t;
79 mrvl_pp2_if_t *interfaces;
80 mrvl_pp2_per_thread_data_t *per_thread_data;
82 /* API message ID base */
86 extern vnet_device_class_t mrvl_pp2_device_class;
87 extern mrvl_pp2_main_t mrvl_pp2_main;
99 } mrvl_pp2_create_if_args_t;
101 void mrvl_pp2_create_if (mrvl_pp2_create_if_args_t * args);
102 void mrvl_pp2_delete_if (mrvl_pp2_if_t * dfif);
103 clib_error_t *mrvl_pp2_plugin_api_hookup (vlib_main_t * vm);
107 #define foreach_mrvl_pp2_tx_func_error \
108 _(NO_FREE_SLOTS, "no free tx slots") \
109 _(PPIO_SEND, "pp2_ppio_send errors") \
110 _(PPIO_GET_NUM_OUTQ_DONE, "pp2_ppio_get_num_outq_done errors")
114 #define _(f,s) MRVL_PP2_TX_ERROR_##f,
115 foreach_mrvl_pp2_tx_func_error
118 } mrvl_pp2_tx_func_error_t;
120 uword mrvl_pp2_interface_tx (vlib_main_t * vm, vlib_node_runtime_t * node,
121 vlib_frame_t * frame);
129 struct pp2_ppio_desc desc;
130 } mrvl_pp2_input_trace_t;
132 extern vlib_node_registration_t mrvl_pp2_input_node;
135 format_function_t format_mrvl_pp2_input_trace;
136 format_function_t format_mrvl_pp2_interface;
137 format_function_t format_mrvl_pp2_interface_name;
141 * fd.io coding-style-patch-verification: ON
144 * eval: (c-set-style "gnu")