2 * Copyright (c) 2020 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #include <vnet/vnet.h>
17 #include <vppinfra/linux/sysfs.h>
18 #include <perfmon/perfmon.h>
19 #include <perfmon/intel/core.h>
22 format_intel_core_cache_hit_miss (u8 *s, va_list *args)
24 perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
25 int row = va_arg (*args, int);
30 s = format (s, "%0.2f", (f64) ns->value[0] / ns->n_packets);
33 s = format (s, "%0.2f", (f64) ns->value[1] / ns->n_packets);
38 (f64) (ns->value[1] - clib_min (ns->value[1], ns->value[2])) /
42 s = format (s, "%0.2f", (f64) ns->value[2] / ns->n_packets);
47 (f64) (ns->value[2] - clib_min (ns->value[2], ns->value[3])) /
51 s = format (s, "%0.2f", (f64) ns->value[3] / ns->n_packets);
58 PERFMON_REGISTER_BUNDLE (intel_core_cache_miss_hit) = {
59 .name = "cache-hierarchy",
60 .description = "cache hits and misses",
61 .source = "intel-core",
62 .type = PERFMON_BUNDLE_TYPE_NODE,
64 .events[0] = INTEL_CORE_E_MEM_LOAD_RETIRED_L1_HIT,
65 .events[1] = INTEL_CORE_E_MEM_LOAD_RETIRED_L1_MISS,
66 .events[2] = INTEL_CORE_E_MEM_LOAD_RETIRED_L2_MISS,
67 .events[3] = INTEL_CORE_E_MEM_LOAD_RETIRED_L3_MISS,
69 .format_fn = format_intel_core_cache_hit_miss,
70 .column_headers = PERFMON_STRINGS ("L1 hit/pkt", "L1 miss/pkt", "L2 hit/pkt",
71 "L2 miss/pkt", "L3 hit/pkt",