2 * Copyright (c) 2020 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #include <perfmon/perfmon.h>
17 #include <perfmon/intel/uncore.h>
18 #include <vlib/pci/pci.h>
19 #include <vppinfra/format.h>
20 #include <linux/limits.h>
32 static const char *procfs_pci_path = "/proc/bus/pci";
34 #define PCM_INTEL_PCI_VENDOR_ID 0x8086
35 #define SNR_ICX_SAD_CONTROL_CFG_OFFSET 0x3F4
36 #define SNR_ICX_MESH2IIO_MMAP_DID 0x09A2
38 static const u8 icx_sad_to_pmu_id_mapping[] = { 5, 0, 1, 2, 3, 4 };
40 static const char *iio_bw_footer_message =
41 "* this bundle currently only measures x8 and x16 PCIe devices on Port #0\n"
42 "or Port #2. Please see the \"Intel® Xeon® Processor Scalable Memory\n"
43 "Family Uncore Performance Monitoring Reference Manual(336274)\"\n"
44 "Section 2.4 for more information.";
47 get_sad_ctrl_cfg (vlib_pci_addr_t *addr)
51 u8 *dev_node_name = format (0, "%s/%02x/%02x.%x", procfs_pci_path, addr->bus,
52 addr->slot, addr->function);
54 fd = open ((char *) dev_node_name, O_RDWR);
58 if (pread (fd, &value, sizeof (u32), SNR_ICX_SAD_CONTROL_CFG_OFFSET) <
68 get_bus_to_sad_mappings (vlib_main_t *vm, index_t **ph, iio_uncore_sad_t **pp)
71 iio_uncore_sad_t *p = 0, *e = 0;
72 vlib_pci_addr_t *addr = 0, *addrs;
74 addrs = vlib_pci_get_all_dev_addrs ();
76 vec_foreach (addr, addrs)
78 vlib_pci_device_info_t *d;
79 d = vlib_pci_get_device_info (vm, addr, 0);
84 if (d->vendor_id == PCM_INTEL_PCI_VENDOR_ID &&
85 d->device_id == SNR_ICX_MESH2IIO_MMAP_DID)
88 u32 sad_ctrl_cfg = get_sad_ctrl_cfg (addr);
89 if (sad_ctrl_cfg == 0xFFFFFFFF)
91 vlib_pci_free_device_info (d);
97 e->socket_id = (sad_ctrl_cfg & 0xf);
98 e->sad_id = (sad_ctrl_cfg >> 4) & 0x7;
99 e->iio_unit_id = icx_sad_to_pmu_id_mapping[e->sad_id];
101 hash_set (h, addr->bus, e - p);
104 vlib_pci_free_device_info (d);
116 format_stack_socket (u8 *s, va_list *va)
118 iio_uncore_sad_t *e, *p = va_arg (*va, iio_uncore_sad_t *);
119 index_t *h = va_arg (*va, index_t *);
120 vlib_pci_addr_t root_bus, *addr = va_arg (*va, vlib_pci_addr_t *);
121 clib_error_t *err = vlib_pci_get_device_root_bus (addr, &root_bus);
124 clib_error_free (err);
128 uword *pu = hash_get (h, root_bus.bus);
129 e = pool_elt_at_index (p, (index_t) pu[0]);
133 s = format (s, "IIO%u/%u", e->socket_id, e->iio_unit_id);
137 static clib_error_t *
138 init_intel_uncore_iio_bw (vlib_main_t *vm, struct perfmon_bundle *b)
141 iio_uncore_sad_t *p = 0;
142 vlib_pci_addr_t *addr = 0, *addrs;
145 get_bus_to_sad_mappings (vm, &h, &p);
147 s = format (0, "%-10s%-5s%-13s%-12s%-14s%-16s%s\n", "Stack", "Port",
148 "Address", "VID:PID", "Link Speed", "Driver", "Product Name");
150 addrs = vlib_pci_get_all_dev_addrs ();
152 vec_foreach (addr, addrs)
154 vlib_pci_device_info_t *d;
155 d = vlib_pci_get_device_info (vm, addr, 0);
160 if (d->device_class != PCI_CLASS_NETWORK_ETHERNET)
164 s, "%-10U%-5U%-13U%04x:%04x %-14U%-16s%v\n", format_stack_socket, p,
165 h, addr, format_vlib_pci_link_port, d, format_vlib_pci_addr, addr,
166 d->vendor_id, d->device_id, format_vlib_pci_link_speed, d,
167 d->driver_name ? (char *) d->driver_name : "", d->product_name);
169 vlib_pci_free_device_info (d);
172 b->footer = (char *) format (s, "\n%s", iio_bw_footer_message);
182 format_intel_uncore_iio_bw (u8 *s, va_list *args)
184 perfmon_reading_t *r = va_arg (*args, perfmon_reading_t *);
185 int col = va_arg (*args, int);
186 f64 tr = r->time_running * 1e-9;
192 s = format (s, "%9.2f", tr);
197 value = r->value[col - 1] * 4 / tr;
200 s = format (s, "%9.0fM", value * 1e-6);
201 else if (value > 1.0e3)
202 s = format (s, "%9.0fK", value * 1e-3);
204 s = format (s, "%9.0f ", value);
214 * This bundle is currently only supported and tested on Intel Icelake.
219 return clib_cpu_supports_avx512_bitalg () && !clib_cpu_supports_movdir64b ();
222 static perfmon_cpu_supports_t iio_bw_cpu_supports[] = {
223 { is_icelake, PERFMON_BUNDLE_TYPE_SYSTEM }
226 PERFMON_REGISTER_BUNDLE (intel_uncore_iio_bw_pci) = {
227 .name = "iio-bandwidth-pci",
228 .description = "pci iio memory reads and writes per iio stack *",
229 .source = "intel-uncore",
230 .events[0] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_OF_CPU_PART0_RD,
231 .events[1] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART0_WR,
232 .events[2] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_RD,
233 .events[3] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_WR,
235 .cpu_supports = iio_bw_cpu_supports,
236 .n_cpu_supports = ARRAY_LEN (iio_bw_cpu_supports),
237 .format_fn = format_intel_uncore_iio_bw,
238 .init_fn = init_intel_uncore_iio_bw,
239 .column_headers = PERFMON_STRINGS ("RunTime", "PCIe Rd/P0", "PCIe Wr/P0",
240 "PCIe Rd/P2", "PCIe Wr/P2")
243 PERFMON_REGISTER_BUNDLE (intel_uncore_iio_bw_cpu) = {
244 .name = "iio-bandwidth-cpu",
245 .description = "cpu iio memory reads and writes per iio stack *",
246 .source = "intel-uncore",
247 .events[0] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART0_RD,
248 .events[1] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART0_WR,
249 .events[2] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_RD,
250 .events[3] = INTEL_UNCORE_E_IIO_UNC_IIO_DATA_REQ_BY_CPU_PART2_WR,
252 .cpu_supports = iio_bw_cpu_supports,
253 .n_cpu_supports = ARRAY_LEN (iio_bw_cpu_supports),
254 .format_fn = format_intel_uncore_iio_bw,
255 .init_fn = init_intel_uncore_iio_bw,
256 .column_headers = PERFMON_STRINGS ("RunTime", "CPU Rd/P0", "CPU Wr/P0",
257 "CPU Rd/P2", "CPU Wr/P2")