src/plugins/perfmon/intel/bundle/membw_bound.c

   1 /*
   2  * Copyright (c) 2021 Intel and/or its affiliates.
   3  * Licensed under the Apache License, Version 2.0 (the "License");
   4  * you may not use this file except in compliance with the License.
   5  * You may obtain a copy of the License at:
   6  *
   7  *     http://www.apache.org/licenses/LICENSE-2.0
   8  *
   9  * Unless required by applicable law or agreed to in writing, software
  10  * distributed under the License is distributed on an "AS IS" BASIS,
  11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12  * See the License for the specific language governing permissions and
  13  * limitations under the License.
  14  */
  15
  16 #include <perfmon/perfmon.h>
  17 #include <perfmon/intel/core.h>
  18
  19 static u8 *
  20 format_intel_membw_bound (u8 *s, va_list *args)
  21 {
  22   perfmon_node_stats_t *ss = va_arg (*args, perfmon_node_stats_t *);
  23   int row = va_arg (*args, int);
  24   f64 sv = 0;
  25
  26   if (!ss->n_packets)
  27     return s;
  28
  29   sv = ss->value[row] / ss->n_packets;
  30
  31   s = format (s, "%5.0f", sv);
  32
  33   return s;
  34 }
  35
  36 static perfmon_cpu_supports_t membw_bound_cpu_supports[] = {
  37   { clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE },
  38 };
  39
  40 PERFMON_REGISTER_BUNDLE (intel_core_membw_bound) = {
  41   .name = "membw-bound",
  42   .description = "memory bandwidth boundedness",
  43   .source = "intel-core",
  44   .events[0] = INTEL_CORE_E_CPU_CLK_UNHALTED_THREAD_P,        /* FIXED */
  45   .events[1] = INTEL_CORE_E_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE, /*CMask: 0xFF*/
  46   .events[2] = INTEL_CORE_E_CYCLE_ACTIVITY_STALLS_MEM_ANY,    /*CMask: 0xFF*/
  47   .events[3] = INTEL_CORE_E_CYCLE_ACTIVITY_STALLS_L1D_MISS,   /*CMask: 0xF*/
  48   .events[4] = INTEL_CORE_E_L1D_PEND_MISS_FB_FULL,            /*CMask: 0xF*/
  49   .events[5] = INTEL_CORE_E_CYCLE_ACTIVITY_STALLS_L3_MISS,    /*CMask: 0xF*/
  50   .events[6] = INTEL_CORE_E_SQ_MISC_SQ_FULL,                  /*CMask: 0xF*/
  51   .n_events = 7,
  52   .format_fn = format_intel_membw_bound,
  53   .cpu_supports = membw_bound_cpu_supports,
  54   .n_cpu_supports = ARRAY_LEN (membw_bound_cpu_supports),
  55   .column_headers = PERFMON_STRINGS ("Cycles/Packet", "Cycles Stall/Packet",
  56                                      "Mem Stall/Packet",
  57                                      "L1D Miss Stall/Packet", "FB Full/Packet",
  58                                      "L3 Miss Stall/Packet", "SQ Full/Packet"),
  59 };