2 * Copyright (c) 2021 Intel and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #include <vnet/vnet.h>
17 #include <vppinfra/math.h>
18 #include <perfmon/perfmon.h>
19 #include <perfmon/intel/core.h>
21 #define GET_METRIC(m, i) (((m) >> (i * 8)) & 0xff)
22 #define GET_RATIO(m, i) (((m) >> (i * 32)) & 0xffffffff)
23 #define RDPMC_SLOTS (1 << 30) /* fixed slots */
24 #define RDPMC_METRICS (1 << 29) /* l1 & l2 metric counters */
26 #define FIXED_COUNTER_SLOTS 3
27 #define METRIC_COUNTER_TOPDOWN_L1_L2 0
31 TOPDOWN_E_RETIRING = 0,
48 TOPDOWN_E_RDPMC_SLOTS = 0,
49 TOPDOWN_E_RDPMC_METRICS,
52 typedef f64 (topdown_lvl1_parse_fn_t) (void *, topdown_e_t);
54 /* Parse thread level states from perfmon_reading */
55 static_always_inline f64
56 topdown_lvl1_perf_reading (void *ps, topdown_e_t e)
58 perfmon_reading_t *ss = (perfmon_reading_t *) ps;
60 /* slots are at value[0], everthing else follows at +1 */
61 return ((f64) ss->value[e + 1] / ss->value[0]) * 100;
64 static_always_inline f64
65 topdown_lvl1_rdpmc_metric (void *ps, topdown_e_t e)
67 perfmon_node_stats_t *ss = (perfmon_node_stats_t *) ps;
69 ss->t[0].value[TOPDOWN_E_RDPMC_SLOTS] *
70 ((f64) GET_METRIC (ss->t[0].value[TOPDOWN_E_RDPMC_METRICS], e) / 0xff);
72 ss->t[1].value[TOPDOWN_E_RDPMC_SLOTS] *
73 ((f64) GET_METRIC (ss->t[1].value[TOPDOWN_E_RDPMC_METRICS], e) / 0xff);
74 u64 slots_delta = ss->t[1].value[TOPDOWN_E_RDPMC_SLOTS] -
75 ss->t[0].value[TOPDOWN_E_RDPMC_SLOTS];
77 slots_t1 = slots_t1 - slots_t0;
79 return (slots_t1 / slots_delta) * 100;
83 format_topdown_lvl1 (u8 *s, va_list *args)
85 void *ps = va_arg (*args, void *);
86 u64 idx = va_arg (*args, int);
87 perfmon_bundle_type_t type = va_arg (*args, perfmon_bundle_type_t);
90 topdown_lvl1_parse_fn_t *parse_fn,
91 *parse_fns[PERFMON_BUNDLE_TYPE_MAX] = { 0, topdown_lvl1_rdpmc_metric,
92 topdown_lvl1_perf_reading, 0 };
93 parse_fn = parse_fns[type];
100 parse_fn (ps, TOPDOWN_E_BAD_SPEC) + parse_fn (ps, TOPDOWN_E_RETIRING);
104 parse_fn (ps, TOPDOWN_E_BE_BOUND) + parse_fn (ps, TOPDOWN_E_FE_BOUND);
107 sv = parse_fn (ps, (topdown_e_t) idx - 2);
111 s = format (s, "%f", sv);
116 static perfmon_cpu_supports_t topdown_lvl1_cpu_supports[] = {
117 /* Intel ICX supports papi/thread or rdpmc/node */
118 { clib_cpu_supports_avx512_bitalg, PERFMON_BUNDLE_TYPE_NODE_OR_THREAD }
121 PERFMON_REGISTER_BUNDLE (topdown_lvl1_metric) = {
122 .name = "topdown-level1",
123 .description = "Top-down Microarchitecture Analysis Level 1",
124 .source = "intel-core",
125 .events[0] = INTEL_CORE_E_TOPDOWN_SLOTS,
126 .events[1] = INTEL_CORE_E_TOPDOWN_L1_RETIRING_METRIC,
127 .events[2] = INTEL_CORE_E_TOPDOWN_L1_BAD_SPEC_METRIC,
128 .events[3] = INTEL_CORE_E_TOPDOWN_L1_FE_BOUND_METRIC,
129 .events[4] = INTEL_CORE_E_TOPDOWN_L1_BE_BOUND_METRIC,
131 .preserve_samples = 0x1F,
132 .cpu_supports = topdown_lvl1_cpu_supports,
133 .n_cpu_supports = ARRAY_LEN (topdown_lvl1_cpu_supports),
134 .format_fn = format_topdown_lvl1,
135 .column_headers = PERFMON_STRINGS ("% NS", "% ST", "% NS.RT", "% NS.BS",
136 "% ST.FE", "% ST.BE"),
137 .footer = "Not Stalled (NS),STalled (ST),\n"
138 " Retiring (RT), Bad Speculation (BS),\n"
139 " FrontEnd bound (FE), BackEnd bound (BE)",
142 /* Convert the TopDown enum to the perf reading index */
143 #define TO_LVL2_PERF_IDX(e) \
145 u8 to_idx[TOPDOWN_E_MAX] = { 0, 0, 0, 0, 5, 5, 6, 6, 7, 7, 8, 8 }; \
149 /* Parse thread level stats from perfmon_reading */
150 static_always_inline f64
151 topdown_lvl2_perf_reading (void *ps, topdown_e_t e)
153 perfmon_reading_t *ss = (perfmon_reading_t *) ps;
154 u64 value = ss->value[TO_LVL2_PERF_IDX (e)];
156 /* If it is an L1 metric, call L1 format */
157 if (TOPDOWN_E_BE_BOUND >= e)
159 return topdown_lvl1_perf_reading (ps, e);
162 /* all the odd metrics, are inferred from even and L1 metrics */
165 topdown_e_t e1 = TO_LVL2_PERF_IDX (e) - 4;
166 value = ss->value[e1] - value;
169 return (f64) value / ss->value[0] * 100;
172 /* Convert the TopDown enum to the rdpmc metric byte position */
173 #define TO_LVL2_METRIC_BYTE(e) \
175 u8 to_metric[TOPDOWN_E_MAX] = { 0, 0, 0, 0, 4, 4, 5, 5, 6, 6, 7, 7 }; \
179 /* Convert the TopDown L2 enum to the reference TopDown L1 enum */
180 #define TO_LVL1_REF(e) \
182 u8 to_lvl1[TOPDOWN_E_MAX] = { -1, \
186 TOPDOWN_E_RETIRING, \
187 TOPDOWN_E_RETIRING, \
188 TOPDOWN_E_BAD_SPEC, \
189 TOPDOWN_E_BAD_SPEC, \
190 TOPDOWN_E_FE_BOUND, \
191 TOPDOWN_E_FE_BOUND, \
192 TOPDOWN_E_BE_BOUND, \
193 TOPDOWN_E_BE_BOUND }; \
197 static_always_inline f64
198 topdown_lvl2_rdpmc_metric (void *ps, topdown_e_t e)
202 /* If it is an L1 metric, call L1 format */
203 if (TOPDOWN_E_BE_BOUND >= e)
205 return topdown_lvl1_rdpmc_metric (ps, e);
208 /* all the odd metrics, are inferred from even and L1 metrics */
211 /* get the L1 reference metric */
212 l1_value = topdown_lvl1_rdpmc_metric (ps, TO_LVL1_REF (e));
215 /* calculate the l2 metric */
217 fabs (l1_value - topdown_lvl1_rdpmc_metric (ps, TO_LVL2_METRIC_BYTE (e)));
222 format_topdown_lvl2 (u8 *s, va_list *args)
224 void *ps = va_arg (*args, void *);
225 u64 idx = va_arg (*args, int);
226 perfmon_bundle_type_t type = va_arg (*args, perfmon_bundle_type_t);
229 topdown_lvl1_parse_fn_t *parse_fn,
230 *parse_fns[PERFMON_BUNDLE_TYPE_MAX] = { 0, topdown_lvl2_rdpmc_metric,
231 topdown_lvl2_perf_reading, 0 };
233 parse_fn = parse_fns[type];
236 sv = parse_fn (ps, (topdown_e_t) idx);
237 s = format (s, "%f", sv);
242 static perfmon_cpu_supports_t topdown_lvl2_cpu_supports[] = {
243 /* Intel SPR supports papi/thread or rdpmc/node */
244 { clib_cpu_supports_avx512_fp16, PERFMON_BUNDLE_TYPE_NODE_OR_THREAD }
247 PERFMON_REGISTER_BUNDLE (topdown_lvl2_metric) = {
248 .name = "topdown-level2",
249 .description = "Top-down Microarchitecture Analysis Level 2",
250 .source = "intel-core",
251 .events[0] = INTEL_CORE_E_TOPDOWN_SLOTS,
252 .events[1] = INTEL_CORE_E_TOPDOWN_L1_RETIRING_METRIC,
253 .events[2] = INTEL_CORE_E_TOPDOWN_L1_BAD_SPEC_METRIC,
254 .events[3] = INTEL_CORE_E_TOPDOWN_L1_FE_BOUND_METRIC,
255 .events[4] = INTEL_CORE_E_TOPDOWN_L1_BE_BOUND_METRIC,
256 .events[5] = INTEL_CORE_E_TOPDOWN_L2_HEAVYOPS_METRIC,
257 .events[6] = INTEL_CORE_E_TOPDOWN_L2_BMISPRED_METRIC,
258 .events[7] = INTEL_CORE_E_TOPDOWN_L2_FETCHLAT_METRIC,
259 .events[8] = INTEL_CORE_E_TOPDOWN_L2_MEMBOUND_METRIC,
261 .preserve_samples = 0x1FF,
262 .cpu_supports = topdown_lvl2_cpu_supports,
263 .n_cpu_supports = ARRAY_LEN (topdown_lvl2_cpu_supports),
264 .format_fn = format_topdown_lvl2,
265 .column_headers = PERFMON_STRINGS ("% RT", "% BS", "% FE", "% BE", "% RT.HO",
266 "% RT.LO", "% BS.BM", "% BS.MC",
267 "% FE.FL", "% FE.FB", "% BE.MB",
269 .footer = "Retiring (RT), Bad Speculation (BS),\n"
270 " FrontEnd bound (1FE), BackEnd bound (BE),\n"
271 " Light Operations (LO), Heavy Operations (HO),\n"
272 " Branch Misprediction (BM), Machine Clears (MC),\n"
273 " Fetch Latency (FL), Fetch Bandwidth (FB),\n"
274 " Memory Bound (MB), Core Bound (CB)",