2 * Copyright (c) 2020 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #ifndef __perfmon_intel_h
17 #define __perfmon_intel_h
19 #define PERF_INTEL_CODE(event, umask, edge, any, inv, cmask) \
20 ((event) | (umask) << 8 | (edge) << 18 | (any) << 21 | (inv) << 23 | \
23 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
24 * counter_unit, name, suffix, description */
25 #define foreach_perf_intel_peusdo_event \
26 _ (0x00, 0x80, 0, 0, 0, 0x00, TOPDOWN, L1_RETIRING_METRIC, \
27 "TMA retiring slots for an unhalted logical processor.") \
28 _ (0x00, 0x81, 0, 0, 0, 0x00, TOPDOWN, L1_BAD_SPEC_METRIC, \
29 "TMA bad spec slots or an unhalted logical processor.") \
30 _ (0x00, 0x82, 0, 0, 0, 0x00, TOPDOWN, L1_FE_BOUND_METRIC, \
31 "TMA fe bound slots for an unhalted logical processor.") \
32 _ (0x00, 0x83, 0, 0, 0, 0x00, TOPDOWN, L1_BE_BOUND_METRIC, \
33 "TMA be bound slots for an unhalted logical processor.") \
34 _ (0x00, 0x84, 0, 0, 0, 0x00, TOPDOWN, L2_HEAVYOPS_METRIC, \
35 "TMA heavy operations for an unhalted logical processor.") \
36 _ (0x00, 0x85, 0, 0, 0, 0x00, TOPDOWN, L2_BMISPRED_METRIC, \
37 "TMA branch misprediction slots or an unhalted logical processor.") \
38 _ (0x00, 0x86, 0, 0, 0, 0x00, TOPDOWN, L2_FETCHLAT_METRIC, \
39 "TMA fetch latency slots for an unhalted logical processor.") \
40 _ (0x00, 0x87, 0, 0, 0, 0x00, TOPDOWN, L2_MEMBOUND_METRIC, \
41 "TMA mem bound slots for an unhalted logical processor.")
43 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
44 * counter_unit, name, suffix, description */
45 #define foreach_perf_intel_tremont_event \
46 _ (0xc2, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_RETIRING_TREMONT, \
47 "TMA retiring slots for an unhalted logical processor.") \
48 _ (0x71, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_FE_BOUND_TREMONT, \
49 "TMA fe bound slots for an unhalted logical processor.") \
50 _ (0x73, 0x06, 0, 0, 0, 0x00, TOPDOWN, L1_BAD_SPEC_TREMONT, \
51 "TMA bad spec slots or an unhalted logical processor.") \
52 _ (0x74, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_BE_BOUND_TREMONT, \
53 "TMA be bound slots for an unhalted logical processor.")
55 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
56 * counter_unit, name, suffix, description */
57 #define foreach_perf_intel_core_event \
58 _ (0x00, 0x02, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD, \
59 "Core cycles when the thread is not in halt state") \
60 _ (0x00, 0x03, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, REF_TSC, \
61 "Reference cycles when the core is not in halt state.") \
62 _ (0x00, 0x04, 0, 0, 0, 0x00, TOPDOWN, SLOTS, \
63 "TMA slots available for an unhalted logical processor.") \
64 _ (0x03, 0x02, 0, 0, 0, 0x00, LD_BLOCKS, STORE_FORWARD, \
65 "Loads blocked due to overlapping with a preceding store that cannot be" \
67 _ (0x03, 0x08, 0, 0, 0, 0x00, LD_BLOCKS, NO_SR, \
68 "The number of times that split load operations are temporarily " \
70 "because all resources for handling the split accesses are in use.") \
71 _ (0x07, 0x01, 0, 0, 0, 0x00, LD_BLOCKS_PARTIAL, ADDRESS_ALIAS, \
72 "False dependencies in MOB due to partial compare on address.") \
73 _ (0x08, 0x01, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, MISS_CAUSES_A_WALK, \
74 "Load misses in all DTLB levels that cause page walks") \
75 _ (0x08, 0x02, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_4K, \
76 "Page walk completed due to a demand data load to a 4K page") \
77 _ (0x08, 0x04, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_2M_4M, \
78 "Page walk completed due to a demand data load to a 2M/4M page") \
79 _ (0x08, 0x08, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_1G, \
80 "Page walk completed due to a demand data load to a 1G page") \
81 _ (0x08, 0x0E, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED, \
82 "Load miss in all TLB levels causes a page walk that completes. (All " \
84 _ (0x08, 0x10, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_PENDING, \
85 "Counts 1 per cycle for each PMH that is busy with a page walk for a " \
86 "load. EPT page walk duration are excluded in Skylake.") \
87 _ (0x08, 0x20, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, STLB_HIT, \
88 "Loads that miss the DTLB and hit the STLB.") \
89 _ (0x0D, 0x01, 0, 0, 0, 0x00, INT_MISC, RECOVERY_CYCLES, \
90 "Core cycles the allocator was stalled due to recovery from earlier " \
91 "clear event for this thread (e.g. misprediction or memory nuke)") \
92 _ (0x0D, 0x10, 0, 0, 0, 0x00, INT_MISC, UOP_DROPPING, \
93 "Estimated number of Top-down Microarchitecture Analysis slots that got" \
94 " due to non front-end reasons") \
95 _ (0x0D, 0x80, 0, 0, 0, 0x00, INT_MISC, CLEAR_RESTEER_CYCLES, \
96 "Counts cycles after recovery from a branch misprediction or machine" \
97 "clear till the first uop is issued from the resteered path.") \
98 _ (0x0E, 0x01, 0, 0, 0, 0x00, UOPS_ISSUED, ANY, \
99 "Uops that Resource Allocation Table (RAT) issues to Reservation " \
101 _ (0x28, 0x07, 0, 0, 0, 0x00, CORE_POWER, LVL0_TURBO_LICENSE, \
102 "Core cycles where the core was running in a manner where Turbo may be " \
103 "clipped to the Non-AVX turbo schedule.") \
104 _ (0x28, 0x18, 0, 0, 0, 0x00, CORE_POWER, LVL1_TURBO_LICENSE, \
105 "Core cycles where the core was running in a manner where Turbo may be " \
106 "clipped to the AVX2 turbo schedule.") \
107 _ (0x28, 0x20, 0, 0, 0, 0x00, CORE_POWER, LVL2_TURBO_LICENSE, \
108 "Core cycles where the core was running in a manner where Turbo may be " \
109 "clipped to the AVX512 turbo schedule.") \
110 _ (0x28, 0x40, 0, 0, 0, 0x00, CORE_POWER, THROTTLE, \
111 "Core cycles the core was throttled due to a pending power level " \
113 _ (0x3C, 0x00, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P, \
114 "Thread cycles when thread is not in halt state") \
115 _ (0x3C, 0x00, 0, 1, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P_ANY, \
116 "Core cycles when at least one thread on the physical core is not in " \
118 _ (0x3C, 0x00, 1, 0, 0, 0x01, CPU_CLK_UNHALTED, RING0_TRANS, \
119 "Counts when there is a transition from ring 1, 2 or 3 to ring 0.") \
120 _ (0x48, 0x01, 0, 0, 0, 0x01, L1D_PEND_MISS, PENDING_CYCLES, \
121 "Cycles with L1D load Misses outstanding.") \
122 _ (0x48, 0x01, 0, 0, 0, 0x00, L1D_PEND_MISS, PENDING, \
123 "L1D miss outstandings duration in cycles") \
124 _ (0x48, 0x02, 0, 0, 0, 0x00, L1D_PEND_MISS, FB_FULL, \
125 "Number of times a request needed a FB entry but there was no entry " \
126 "available for it. That is the FB unavailability was dominant reason " \
127 "for blocking the request. A request includes cacheable/uncacheable " \
128 "demands that is load, store or SW prefetch.") \
129 _ (0x51, 0x01, 0, 0, 0, 0x00, L1D, REPLACEMENT, \
130 "L1D data line replacements") \
131 _ (0x51, 0x04, 0, 0, 0, 0x00, L1D, M_EVICT, "L1D data line evictions") \
132 _ (0x79, 0x04, 0, 0, 0, 0x00, IDQ, MITE_UOPS, \
133 "Counts the number of uops delivered to Instruction Decode Queue (IDQ) " \
134 "from the MITE path.") \
135 _ (0x79, 0x08, 0, 0, 0, 0x00, IDQ, DSB_UOPS, \
136 "Counts the number of uops delivered to Instruction Decode Queue (IDQ) " \
137 "from the Decode Stream Buffer (DSB) path.") \
138 _ (0x79, 0x30, 0, 0, 0, 0x00, IDQ, MS_UOPS, \
139 "Counts the number of uops delivered to Instruction Decode Queue (IDQ) " \
140 "from the Microcode Sequencer (MS) path.") \
141 _ (0x79, 0x30, 1, 0, 0, 0x01, IDQ, MS_SWITCHES, \
142 "Number of switches from DSB or MITE to the MS") \
144 0x80, 0x04, 0, 0, 0, 0x00, ICACHE_16B, IFDATA_STALL, \
145 "Cycles where a code fetch is stalled due to L1 instruction cache miss.") \
146 _ (0x83, 0x04, 0, 0, 0, 0x00, ICACHE_64B, IFTAG_STALL, \
147 "Cycles where a code fetch is stalled due to L1 instruction cache tag " \
149 _ (0x83, 0x02, 0, 0, 0, 0x00, ICACHE_64B, IFTAG_MISS, \
150 "Instruction fetch tag lookups that miss in the instruction cache " \
151 "(L1I). Counts at 64-byte cache-line granularity.") \
152 _ (0x9C, 0x01, 0, 0, 0, 0x05, IDQ_UOPS_NOT_DELIVERED, CORE, \
153 "Uops not delivered to Resource Allocation Table (RAT) per thread when " \
154 "backend of the machine is not stalled") \
155 _ (0xA1, 0x01, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_0, \
156 "Number of uops executed on port 0") \
157 _ (0xA1, 0x02, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_1, \
158 "Number of uops executed on port 1") \
159 _ (0xA1, 0x04, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_2_3, \
160 "Number of uops executed on port 2 and 3") \
161 _ (0xA1, 0x10, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_4_9, \
162 "Number of uops executed on port 4 and 9") \
163 _ (0xA1, 0x20, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_5, \
164 "Number of uops executed on port 5") \
165 _ (0xA1, 0x40, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_6, \
166 "Number of uops executed on port 6") \
167 _ (0xA1, 0x80, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_7_8, \
168 "Number of uops executed on port 7 and 8") \
169 _ (0xA2, 0x08, 0, 0, 0, 0x00, RESOURCE_STALLS, SB, \
170 "Counts allocation stall cycles caused by the store buffer (SB) being " \
171 "full. This counts cycles that the pipeline back-end blocked uop " \
173 "from the front-end.") \
174 _ (0xA3, 0x04, 0, 0, 0, 0x04, CYCLE_ACTIVITY, STALLS_TOTAL, \
175 "Total execution stalls.") \
176 _ (0xA3, 0x05, 0, 0, 0, 0x05, CYCLE_ACTIVITY, STALLS_L2_MISS, \
177 "Execution stalls while L2 cache miss demand load is outstanding") \
178 _ (0xA3, 0x06, 0, 0, 0, 0x06, CYCLE_ACTIVITY, STALLS_L3_MISS, \
179 "Execution stalls while L3 cache miss demand load is outstanding") \
180 _ (0xA3, 0x0C, 0, 0, 0, 0x0C, CYCLE_ACTIVITY, STALLS_L1D_MISS, \
181 "Execution stalls while L1 cache miss demand load is outstanding") \
182 _ (0xA3, 0x14, 0, 0, 0, 0x14, CYCLE_ACTIVITY, STALLS_MEM_ANY, \
183 "Execution stalls while memory subsystem has an outstanding load.") \
184 _ (0xA6, 0x40, 0, 0, 0, 0x02, EXE_ACTIVITY, BOUND_ON_STORES, \
185 "Cycles where the Store Buffer was full and no loads caused an " \
186 "execution stall.") \
187 _ (0xA8, 0x01, 0, 0, 0, 0x00, LSD, UOPS, \
188 "Counts the number of uops delivered to the back-end by the LSD" \
189 "(Loop Stream Detector)") \
190 _ (0xAB, 0x02, 0, 0, 0, 0x00, DSB2MITE_SWITCHES, PENALTY_CYCLES, \
191 "This event counts fetch penalty cycles when a transition occurs from" \
193 _ (0xB1, 0x01, 0, 0, 0, 0x00, UOPS_EXECUTED, THREAD, \
194 "Counts the number of uops to be executed per-thread each cycle.") \
195 _ (0xC0, 0x00, 0, 0, 0, 0x00, INST_RETIRED, ANY_P, \
196 "Number of instructions retired. General Counter - architectural event") \
197 _ (0xC2, 0x02, 0, 0, 0, 0x00, UOPS_RETIRED, RETIRE_SLOTS, \
198 "Retirement slots used.") \
199 _ (0xC4, 0x00, 0, 0, 0, 0x00, BR_INST_RETIRED, ALL_BRANCHES, \
200 "Counts all (macro) branch instructions retired.") \
201 _ (0xC5, 0x00, 0, 0, 0, 0x00, BR_MISP_RETIRED, ALL_BRANCHES, \
202 "All mispredicted macro branch instructions retired.") \
203 _ (0xC4, 0x20, 0, 0, 0, 0x00, BR_INST_RETIRED, NEAR_TAKEN, \
204 "Taken branch instructions retired.") \
205 _ (0xD0, 0x82, 0, 0, 0, 0x00, MEM_INST_RETIRED, ALL_STORES, \
206 "All retired store instructions.") \
207 _ (0xD1, 0x01, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_HIT, \
208 "Retired load instructions with L1 cache hits as data sources") \
209 _ (0xD1, 0x02, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_HIT, \
210 "Retired load instructions with L2 cache hits as data sources") \
211 _ (0xD1, 0x04, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_HIT, \
212 "Retired load instructions with L3 cache hits as data sources") \
213 _ (0xD1, 0x08, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_MISS, \
214 "Retired load instructions missed L1 cache as data sources") \
215 _ (0xD1, 0x10, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_MISS, \
216 "Retired load instructions missed L2 cache as data sources") \
217 _ (0xD1, 0x20, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_MISS, \
218 "Retired load instructions missed L3 cache as data sources") \
219 _ (0xD1, 0x40, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, FB_HIT, \
220 "Retired load instructions which data sources were load missed L1 but " \
221 "hit FB due to preceding miss to the same cache line with data not " \
223 _ (0xD2, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_MISS, \
224 "Retired load instructions which data sources were L3 hit and cross-" \
225 "core snoop missed in on-pkg core cache.") \
226 _ (0xD2, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HIT, \
227 "Retired load instructions which data sources were L3 and cross-core " \
228 "snoop hits in on-pkg core cache") \
229 _ (0xD2, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HITM, \
230 "Retired load instructions which data sources were HitM responses from " \
232 _ (0xD2, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_NONE, \
233 "Retired load instructions which data sources were hits in L3 without " \
235 _ (0xD3, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, LOCAL_DRAM, \
236 "Retired load instructions which data sources missed L3 but serviced " \
238 _ (0xD3, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_DRAM, \
239 "Retired load instructions which data sources missed L3 but serviced " \
240 "from remote dram") \
241 _ (0xD3, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_HITM, \
242 "Retired load instructions whose data sources was remote HITM") \
243 _ (0xD3, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_FWD, \
244 "Retired load instructions whose data sources was forwarded from a " \
246 _ (0xE6, 0x01, 0, 0, 0, 0x00, BACLEARS, ANY, \
247 "Counts the total number when the front end is resteered, mainly when " \
248 "the BPU cannot provide a correct prediction and this is corrected by " \
249 "other branch handling mechanisms at the front end.") \
250 _ (0xEC, 0x02, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, DISTRIBUTED, \
251 "Cycle counts are evenly distributed between active threads in the " \
253 _ (0xF0, 0x40, 0, 0, 0, 0x00, L2_TRANS, L2_WB, \
254 "L2 writebacks that access L2 cache") \
255 _ (0xF1, 0x1F, 0, 0, 0, 0x00, L2_LINES_IN, ALL, \
256 "L2 cache lines filling L2") \
257 _ (0xF4, 0x04, 0, 0, 0, 0x00, SQ_MISC, SQ_FULL, \
258 "Counts the cycles for which the thread is active and the superQ cannot" \
259 "take any more entries.") \
260 _ (0xFE, 0x02, 0, 0, 0, 0x00, IDI_MISC, WB_UPGRADE, \
261 "Counts number of cache lines that are allocated and written back to L3" \
262 " with the intention that they are more likely to be reused shortly") \
263 _ (0xFE, 0x04, 0, 0, 0, 0x00, IDI_MISC, WB_DOWNGRADE, \
264 "Counts number of cache lines that are dropped and not written back to " \
265 "L3 as they are deemed to be less likely to be reused shortly")
269 #define _(event, umask, edge, any, inv, cmask, name, suffix, desc) \
270 INTEL_CORE_E_##name##_##suffix,
271 foreach_perf_intel_core_event foreach_perf_intel_peusdo_event
272 foreach_perf_intel_tremont_event
275 } perf_intel_core_event_t;