2 * Copyright (c) 2020 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #ifndef __perfmon_intel_h
17 #define __perfmon_intel_h
19 #define PERF_INTEL_CODE(event, umask, edge, any, inv, cmask) \
20 ((event) | (umask) << 8 | (edge) << 18 | (any) << 21 | (inv) << 23 | \
23 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
24 * counter_unit, name, suffix, description */
25 #define foreach_perf_intel_peusdo_event \
26 _ (0x00, 0x80, 0, 0, 0, 0x00, TOPDOWN, L1_RETIRING_METRIC, \
27 "TMA retiring slots for an unhalted logical processor.") \
28 _ (0x00, 0x81, 0, 0, 0, 0x00, TOPDOWN, L1_BAD_SPEC_METRIC, \
29 "TMA bad spec slots or an unhalted logical processor.") \
30 _ (0x00, 0x82, 0, 0, 0, 0x00, TOPDOWN, L1_FE_BOUND_METRIC, \
31 "TMA fe bound slots for an unhalted logical processor.") \
32 _ (0x00, 0x83, 0, 0, 0, 0x00, TOPDOWN, L1_BE_BOUND_METRIC, \
33 "TMA be bound slots for an unhalted logical processor.") \
34 _ (0x00, 0x84, 0, 0, 0, 0x00, TOPDOWN, L2_HEAVYOPS_METRIC, \
35 "TMA heavy operations for an unhalted logical processor.") \
36 _ (0x00, 0x85, 0, 0, 0, 0x00, TOPDOWN, L2_BMISPRED_METRIC, \
37 "TMA branch misprediction slots or an unhalted logical processor.") \
38 _ (0x00, 0x86, 0, 0, 0, 0x00, TOPDOWN, L2_FETCHLAT_METRIC, \
39 "TMA fetch latency slots for an unhalted logical processor.") \
40 _ (0x00, 0x87, 0, 0, 0, 0x00, TOPDOWN, L2_MEMBOUND_METRIC, \
41 "TMA mem bound slots for an unhalted logical processor.")
43 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
44 * counter_unit, name, suffix, description */
45 #define foreach_perf_intel_tremont_event \
46 _ (0xc2, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_RETIRING_TREMONT, \
47 "TMA retiring slots for an unhalted logical processor.") \
48 _ (0x71, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_FE_BOUND_TREMONT, \
49 "TMA fe bound slots for an unhalted logical processor.") \
50 _ (0x73, 0x06, 0, 0, 0, 0x00, TOPDOWN, L1_BAD_SPEC_TREMONT, \
51 "TMA bad spec slots or an unhalted logical processor.") \
52 _ (0x74, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_BE_BOUND_TREMONT, \
53 "TMA be bound slots for an unhalted logical processor.")
55 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
56 * counter_unit, name, suffix, description */
57 #define foreach_perf_intel_core_event \
58 _ (0x00, 0x02, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD, \
59 "Core cycles when the thread is not in halt state") \
60 _ (0x00, 0x03, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, REF_TSC, \
61 "Reference cycles when the core is not in halt state.") \
62 _ (0x00, 0x04, 0, 0, 0, 0x00, TOPDOWN, SLOTS, \
63 "TMA slots available for an unhalted logical processor.") \
64 _ (0x03, 0x02, 0, 0, 0, 0x00, LD_BLOCKS, STORE_FORWARD, \
65 "Loads blocked due to overlapping with a preceding store that cannot be" \
67 _ (0x03, 0x08, 0, 0, 0, 0x00, LD_BLOCKS, NO_SR, \
68 "The number of times that split load operations are temporarily " \
70 "because all resources for handling the split accesses are in use.") \
71 _ (0x07, 0x01, 0, 0, 0, 0x00, LD_BLOCKS_PARTIAL, ADDRESS_ALIAS, \
72 "False dependencies in MOB due to partial compare on address.") \
73 _ (0x08, 0x01, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, MISS_CAUSES_A_WALK, \
74 "Load misses in all DTLB levels that cause page walks") \
75 _ (0x08, 0x02, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_4K, \
76 "Page walk completed due to a demand data load to a 4K page") \
77 _ (0x08, 0x04, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_2M_4M, \
78 "Page walk completed due to a demand data load to a 2M/4M page") \
79 _ (0x08, 0x08, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_1G, \
80 "Page walk completed due to a demand data load to a 1G page") \
81 _ (0x08, 0x0E, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED, \
82 "Load miss in all TLB levels causes a page walk that completes. (All " \
84 _ (0x08, 0x10, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_PENDING, \
85 "Counts 1 per cycle for each PMH that is busy with a page walk for a " \
86 "load. EPT page walk duration are excluded in Skylake.") \
87 _ (0x08, 0x20, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, STLB_HIT, \
88 "Loads that miss the DTLB and hit the STLB.") \
89 _ (0x0D, 0x01, 0, 0, 0, 0x00, INT_MISC, RECOVERY_CYCLES, \
90 "Core cycles the allocator was stalled due to recovery from earlier " \
91 "clear event for this thread (e.g. misprediction or memory nuke)") \
92 _ (0x0E, 0x01, 0, 0, 0, 0x00, UOPS_ISSUED, ANY, \
93 "Uops that Resource Allocation Table (RAT) issues to Reservation " \
95 _ (0x28, 0x07, 0, 0, 0, 0x00, CORE_POWER, LVL0_TURBO_LICENSE, \
96 "Core cycles where the core was running in a manner where Turbo may be " \
97 "clipped to the Non-AVX turbo schedule.") \
98 _ (0x28, 0x18, 0, 0, 0, 0x00, CORE_POWER, LVL1_TURBO_LICENSE, \
99 "Core cycles where the core was running in a manner where Turbo may be " \
100 "clipped to the AVX2 turbo schedule.") \
101 _ (0x28, 0x20, 0, 0, 0, 0x00, CORE_POWER, LVL2_TURBO_LICENSE, \
102 "Core cycles where the core was running in a manner where Turbo may be " \
103 "clipped to the AVX512 turbo schedule.") \
104 _ (0x28, 0x40, 0, 0, 0, 0x00, CORE_POWER, THROTTLE, \
105 "Core cycles the core was throttled due to a pending power level " \
107 _ (0x3C, 0x00, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P, \
108 "Thread cycles when thread is not in halt state") \
109 _ (0x3C, 0x00, 0, 1, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P_ANY, \
110 "Core cycles when at least one thread on the physical core is not in " \
112 _ (0x3C, 0x00, 1, 0, 0, 0x01, CPU_CLK_UNHALTED, RING0_TRANS, \
113 "Counts when there is a transition from ring 1, 2 or 3 to ring 0.") \
114 _ (0x48, 0x01, 0, 0, 0, 0x01, L1D_PEND_MISS, PENDING_CYCLES, \
115 "Cycles with L1D load Misses outstanding.") \
116 _ (0x48, 0x01, 0, 0, 0, 0x00, L1D_PEND_MISS, PENDING, \
117 "L1D miss outstandings duration in cycles") \
118 _ (0x48, 0x02, 0, 0, 0, 0x00, L1D_PEND_MISS, FB_FULL, \
119 "Number of times a request needed a FB entry but there was no entry " \
120 "available for it. That is the FB unavailability was dominant reason " \
121 "for blocking the request. A request includes cacheable/uncacheable " \
122 "demands that is load, store or SW prefetch.") \
123 _ (0x51, 0x01, 0, 0, 0, 0x00, L1D, REPLACEMENT, \
124 "L1D data line replacements") \
125 _ (0x51, 0x04, 0, 0, 0, 0x00, L1D, M_EVICT, "L1D data line evictions") \
126 _ (0x83, 0x02, 0, 0, 0, 0x00, ICACHE_64B, IFTAG_MISS, \
127 "Instruction fetch tag lookups that miss in the instruction cache " \
128 "(L1I). Counts at 64-byte cache-line granularity.") \
129 _ (0x9C, 0x01, 0, 0, 0, 0x00, IDQ_UOPS_NOT_DELIVERED, CORE, \
130 "Uops not delivered to Resource Allocation Table (RAT) per thread when " \
131 "backend of the machine is not stalled") \
132 _ (0xA2, 0x08, 0, 0, 0, 0x00, RESOURCE_STALLS, SB, \
133 "Counts allocation stall cycles caused by the store buffer (SB) being " \
134 "full. This counts cycles that the pipeline back-end blocked uop " \
136 "from the front-end.") \
137 _ (0xA3, 0x04, 0, 0, 0, 0x04, CYCLE_ACTIVITY, CYCLES_NO_EXECUTE, \
138 "This event counts cycles during which no instructions were executed in" \
139 " the execution stage of the pipeline.") \
140 _ (0xA3, 0x05, 0, 0, 0, 0x05, CYCLE_ACTIVITY, STALLS_L2_MISS, \
141 "Execution stalls while L2 cache miss demand load is outstanding") \
142 _ (0xA3, 0x06, 0, 0, 0, 0x06, CYCLE_ACTIVITY, STALLS_L3_MISS, \
143 "Execution stalls while L3 cache miss demand load is outstanding") \
144 _ (0xA3, 0x0C, 0, 0, 0, 0x0C, CYCLE_ACTIVITY, STALLS_L1D_MISS, \
145 "Execution stalls while L1 cache miss demand load is outstanding") \
146 _ (0xA3, 0x14, 0, 0, 0, 0x14, CYCLE_ACTIVITY, STALLS_MEM_ANY, \
147 "Execution stalls while memory subsystem has an outstanding load.") \
148 _ (0xC0, 0x00, 0, 0, 0, 0x00, INST_RETIRED, ANY_P, \
149 "Number of instructions retired. General Counter - architectural event") \
150 _ (0xC2, 0x02, 0, 0, 0, 0x00, UOPS_RETIRED, RETIRE_SLOTS, \
151 "Retirement slots used.") \
152 _ (0xC4, 0x00, 0, 0, 0, 0x00, BR_INST_RETIRED, ALL_BRANCHES, \
153 "Counts all (macro) branch instructions retired.") \
154 _ (0xC5, 0x00, 0, 0, 0, 0x00, BR_MISP_RETIRED, ALL_BRANCHES, \
155 "All mispredicted macro branch instructions retired.") \
156 _ (0xC4, 0x20, 0, 0, 0, 0x00, BR_INST_RETIRED, NEAR_TAKEN, \
157 "Taken branch instructions retired.") \
158 _ (0xD0, 0x81, 0, 0, 0, 0x00, MEM_INST_RETIRED, ALL_LOADS, \
159 "All retired load instructions.") \
160 _ (0xD0, 0x82, 0, 0, 0, 0x00, MEM_INST_RETIRED, ALL_STORES, \
161 "All retired store instructions.") \
162 _ (0xD1, 0x01, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_HIT, \
163 "Retired load instructions with L1 cache hits as data sources") \
164 _ (0xD1, 0x02, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_HIT, \
165 "Retired load instructions with L2 cache hits as data sources") \
166 _ (0xD1, 0x04, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_HIT, \
167 "Retired load instructions with L3 cache hits as data sources") \
168 _ (0xD1, 0x08, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_MISS, \
169 "Retired load instructions missed L1 cache as data sources") \
170 _ (0xD1, 0x10, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_MISS, \
171 "Retired load instructions missed L2 cache as data sources") \
172 _ (0xD1, 0x20, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_MISS, \
173 "Retired load instructions missed L3 cache as data sources") \
174 _ (0xD1, 0x40, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, FB_HIT, \
175 "Retired load instructions which data sources were load missed L1 but " \
176 "hit FB due to preceding miss to the same cache line with data not " \
178 _ (0xD2, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_MISS, \
179 "Retired load instructions which data sources were L3 hit and cross-" \
180 "core snoop missed in on-pkg core cache.") \
181 _ (0xD2, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HIT, \
182 "Retired load instructions which data sources were L3 and cross-core " \
183 "snoop hits in on-pkg core cache") \
184 _ (0xD2, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HITM, \
185 "Retired load instructions which data sources were HitM responses from " \
187 _ (0xD2, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_NONE, \
188 "Retired load instructions which data sources were hits in L3 without " \
190 _ (0xD3, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, LOCAL_DRAM, \
191 "Retired load instructions which data sources missed L3 but serviced " \
193 _ (0xD3, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_DRAM, \
194 "Retired load instructions which data sources missed L3 but serviced " \
195 "from remote dram") \
196 _ (0xD3, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_HITM, \
197 "Retired load instructions whose data sources was remote HITM") \
198 _ (0xD3, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_FWD, \
199 "Retired load instructions whose data sources was forwarded from a " \
201 _ (0xF0, 0x40, 0, 0, 0, 0x00, L2_TRANS, L2_WB, \
202 "L2 writebacks that access L2 cache") \
203 _ (0xF1, 0x1F, 0, 0, 0, 0x00, L2_LINES_IN, ALL, \
204 "L2 cache lines filling L2") \
205 _ (0xF4, 0x04, 0, 0, 0, 0x00, SQ_MISC, SQ_FULL, \
206 "Counts the cycles for which the thread is active and the superQ cannot" \
207 "take any more entries.") \
208 _ (0xFE, 0x02, 0, 0, 0, 0x00, IDI_MISC, WB_UPGRADE, \
209 "Counts number of cache lines that are allocated and written back to L3" \
210 " with the intention that they are more likely to be reused shortly") \
211 _ (0xFE, 0x04, 0, 0, 0, 0x00, IDI_MISC, WB_DOWNGRADE, \
212 "Counts number of cache lines that are dropped and not written back to " \
213 "L3 as they are deemed to be less likely to be reused shortly")
217 #define _(event, umask, edge, any, inv, cmask, name, suffix, desc) \
218 INTEL_CORE_E_##name##_##suffix,
219 foreach_perf_intel_core_event foreach_perf_intel_peusdo_event
220 foreach_perf_intel_tremont_event
223 } perf_intel_core_event_t;