2 *------------------------------------------------------------------
3 * Copyright (c) 2018 Cisco and/or its affiliates.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at:
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *------------------------------------------------------------------
21 #include <infiniband/verbs.h>
23 #include <vlib/pci/pci.h>
24 #include <vnet/interface.h>
25 #include <vnet/ethernet/mac_address.h>
26 #include <rdma/rdma_mlx5dv.h>
28 #define foreach_rdma_device_flags \
29 _(0, ERROR, "error") \
30 _(1, ADMIN_UP, "admin-up") \
31 _(2, LINK_UP, "link-up") \
32 _(3, PROMISC, "promiscuous") \
33 _(4, MLX5DV, "mlx5dv") \
34 _(5, STRIDING_RQ, "striding-rq")
38 #define _(a, b, c) RDMA_DEVICE_F_##b = (1 << a),
39 foreach_rdma_device_flags
43 #ifndef MLX5_ETH_L2_INLINE_HEADER_SIZE
44 #define MLX5_ETH_L2_INLINE_HEADER_SIZE 18
49 CLIB_ALIGN_MARK (align0, MLX5_SEND_WQE_BB);
52 struct mlx5_wqe_ctrl_seg ctrl;
61 struct mlx5_wqe_eth_seg eseg;
62 struct mlx5_wqe_data_seg dseg;
64 #define RDMA_MLX5_WQE_SZ sizeof(rdma_mlx5_wqe_t)
65 #define RDMA_MLX5_WQE_DS (RDMA_MLX5_WQE_SZ/sizeof(struct mlx5_wqe_data_seg))
66 STATIC_ASSERT (RDMA_MLX5_WQE_SZ == MLX5_SEND_WQE_BB &&
67 RDMA_MLX5_WQE_SZ % sizeof (struct mlx5_wqe_data_seg) == 0,
72 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
85 mlx5dv_wqe_ds_t *wqes;
86 CLIB_CACHE_LINE_ALIGN_MARK (cacheline1);
93 u32 striding_wqe_tail;
94 u8 log_wqe_sz; /* log-size of a single WQE (in data segments) */
95 u8 log_stride_per_wqe; /* Striding RQ: number of strides in a single WQE */
100 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
102 /* following fields are accessed in datapath */
103 clib_spinlock_t lock;
109 /* ibverb datapath. Cache of cq, sq below */
110 struct ibv_cq *ibv_cq;
111 struct ibv_qp *ibv_qp;
115 /* direct verbs datapath */
116 rdma_mlx5_wqe_t *dv_sq_wqes;
117 volatile u32 *dv_sq_dbrec;
118 volatile u64 *dv_sq_db;
119 struct mlx5_cqe64 *dv_cq_cqes;
120 volatile u32 *dv_cq_dbrec;
124 u32 *bufs; /* vlib_buffer ring buffer */
127 u16 dv_cq_idx; /* monotonic CQE index (valid only for direct verbs) */
128 u8 bufs_log2sz; /* log2 vlib_buffer entries */
129 u8 dv_sq_log2sz:4; /* log2 SQ WQE entries (valid only for direct verbs) */
130 u8 dv_cq_log2sz:4; /* log2 CQ CQE entries (valid only for direct verbs) */
131 STRUCT_MARK (cacheline1);
133 /* WQE template (valid only for direct verbs) */
136 /* end of 2nd 64-bytes cacheline (or 1st 128-bytes cacheline) */
137 STRUCT_MARK (cacheline2);
139 /* fields below are not accessed in datapath */
144 STATIC_ASSERT_OFFSET_OF (rdma_txq_t, cacheline1, 64);
145 STATIC_ASSERT_OFFSET_OF (rdma_txq_t, cacheline2, 128);
147 #define RDMA_TXQ_DV_INVALID_ID 0xffffffff
149 #define RDMA_TXQ_BUF_SZ(txq) (1U << (txq)->bufs_log2sz)
150 #define RDMA_TXQ_DV_SQ_SZ(txq) (1U << (txq)->dv_sq_log2sz)
151 #define RDMA_TXQ_DV_CQ_SZ(txq) (1U << (txq)->dv_cq_log2sz)
153 #define RDMA_TXQ_USED_SZ(head, tail) ((u16)((u16)(tail) - (u16)(head)))
154 #define RDMA_TXQ_AVAIL_SZ(txq, head, tail) ((u16)(RDMA_TXQ_BUF_SZ (txq) - RDMA_TXQ_USED_SZ (head, tail)))
155 #define RDMA_RXQ_MAX_CHAIN_LOG_SZ 3 /* This should NOT be lower than 3! */
156 #define RDMA_RXQ_MAX_CHAIN_SZ (1U << RDMA_RXQ_MAX_CHAIN_LOG_SZ)
157 #define RDMA_RXQ_LEGACY_MODE_MAX_CHAIN_SZ 5
160 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
162 /* following fields are accessed in datapath */
166 u32 per_interface_next_index;
169 u32 lkey; /* cache of mr->lkey */
170 u8 pool; /* buffer pool index */
172 /* fields below are not accessed in datapath */
173 vlib_pci_device_info_t *pci;
176 mac_address_t hwaddr;
177 u32 async_event_clib_file_index;
180 struct ibv_context *ctx;
183 struct ibv_qp *rx_qp4;
184 struct ibv_qp *rx_qp6;
185 struct ibv_rwq_ind_table *rx_rwq_ind_tbl;
186 struct ibv_flow *flow_ucast4;
187 struct ibv_flow *flow_mcast4;
188 struct ibv_flow *flow_ucast6;
189 struct ibv_flow *flow_mcast6;
196 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
199 u16 cqe_flags[VLIB_FRAME_SIZE];
200 u16x8 cqe_flags8[VLIB_FRAME_SIZE / 8];
201 u16x16 cqe_flags16[VLIB_FRAME_SIZE / 16];
203 vlib_buffer_t buffer_template;
204 u32 current_segs[VLIB_FRAME_SIZE];
205 u32 to_free_buffers[VLIB_FRAME_SIZE];
206 } rdma_per_thread_data_t;
210 rdma_per_thread_data_t *per_thread_data;
211 rdma_device_t *devices;
212 vlib_log_class_t log_class;
216 extern rdma_main_t rdma_main;
238 } rdma_create_if_args_t;
240 void rdma_create_if (vlib_main_t * vm, rdma_create_if_args_t * args);
241 void rdma_delete_if (vlib_main_t * vm, rdma_device_t * rd);
243 extern vlib_node_registration_t rdma_input_node;
244 extern vnet_device_class_t rdma_device_class;
246 format_function_t format_rdma_device;
247 format_function_t format_rdma_device_name;
248 format_function_t format_rdma_input_trace;
249 format_function_t format_rdma_rxq;
250 unformat_function_t unformat_rdma_create_if_args;
257 } rdma_input_trace_t;
259 #define foreach_rdma_tx_func_error \
260 _(SEGMENT_SIZE_EXCEEDED, "segment size exceeded") \
261 _(NO_FREE_SLOTS, "no free tx slots") \
262 _(SUBMISSION, "tx submission errors") \
263 _(COMPLETION, "tx completion errors")
267 #define _(f,s) RDMA_TX_ERROR_##f,
268 foreach_rdma_tx_func_error
271 } rdma_tx_func_error_t;
273 #endif /* _RDMA_H_ */
276 * fd.io coding-style-patch-verification: ON
279 * eval: (c-set-style "gnu")