2 *------------------------------------------------------------------
3 * Copyright (c) 2020 Cisco and/or its affiliates.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at:
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *------------------------------------------------------------------
18 #ifndef _RDMA_MLX5DV_H_
19 #define _RDMA_MLX5DV_H_
22 #include <infiniband/mlx5dv.h>
23 #define always_inline static_always_inline
25 /* CQE flags - bits 16-31 of qword at offset 0x1c */
26 #define CQE_FLAG_L4_OK 10
27 #define CQE_FLAG_L3_OK 9
28 #define CQE_FLAG_L2_OK 8
29 #define CQE_FLAG_IP_FRAG 7
30 #define CQE_FLAG_L4_HDR_TYPE(f) (((f) >> 4) & 7)
31 #define CQE_FLAG_L3_HDR_TYPE_SHIFT (2)
32 #define CQE_FLAG_L3_HDR_TYPE_MASK (3 << CQE_FLAG_L3_HDR_TYPE_SHIFT)
33 #define CQE_FLAG_L3_HDR_TYPE(f) (((f) & CQE_FLAG_L3_HDR_TYPE_MASK) >> CQE_FLAG_L3_HDR_TYPE_SHIFT)
34 #define CQE_FLAG_L3_HDR_TYPE_IP4 1
35 #define CQE_FLAG_L3_HDR_TYPE_IP6 2
36 #define CQE_FLAG_IP_EXT_OPTS 1
51 u8 opcode_cqefmt_se_owner;
55 STATIC_ASSERT_SIZEOF (mlx5dv_cqe_t, 64);
73 #define foreach_cqe_rx_field \
74 _(0x1c, 26, 26, l4_ok) \
75 _(0x1c, 25, 25, l3_ok) \
76 _(0x1c, 24, 24, l2_ok) \
77 _(0x1c, 23, 23, ip_frag) \
78 _(0x1c, 22, 20, l4_hdr_type) \
79 _(0x1c, 19, 18, l3_hdr_type) \
80 _(0x1c, 17, 17, ip_ext_opts) \
82 _(0x2c, 31, 0, byte_cnt) \
83 _(0x30, 63, 0, timestamp) \
84 _(0x38, 31, 24, rx_drop_counter) \
85 _(0x38, 23, 0, flow_tag) \
86 _(0x3c, 31, 16, wqe_counter) \
87 _(0x3c, 15, 8, signature) \
88 _(0x3c, 7, 4, opcode) \
89 _(0x3c, 3, 2, cqe_format) \
94 /* inline functions */
97 mlx5_get_u32 (void *start, int offset)
99 return clib_net_to_host_u32 (*(u32 *) (((u8 *) start) + offset));
103 mlx5_get_u64 (void *start, int offset)
105 return clib_net_to_host_u64 (*(u64 *) (((u8 *) start) + offset));
109 mlx5_set_u32 (void *start, int offset, u32 value)
111 (*(u32 *) (((u8 *) start) + offset)) = clib_host_to_net_u32 (value);
115 mlx5_set_u64 (void *start, int offset, u64 value)
117 (*(u64 *) (((u8 *) start) + offset)) = clib_host_to_net_u64 (value);
121 mlx5_set_bits (void *start, int offset, int first, int last, u32 value)
123 u32 mask = (1 << (first - last + 1)) - 1;
124 u32 old = mlx5_get_u32 (start, offset);
125 if ((last == 0) && (first == 31))
127 mlx5_set_u32 (start, offset, value);
130 ASSERT (value == (value & mask));
132 old &= ~(mask << last);
133 mlx5_set_u32 (start, offset, old | value << last);
137 mlx5_get_bits (void *start, int offset, int first, int last)
139 u32 value = mlx5_get_u32 (start, offset);
140 if ((last == 0) && (first == 31))
143 value &= (1 << (first - last + 1)) - 1;
148 #endif /* RDMA_MLX5DV_H */
151 * fd.io coding-style-patch-verification: ON
154 * eval: (c-set-style "gnu")