2 *------------------------------------------------------------------
3 * Copyright (c) 2020 Cisco and/or its affiliates.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at:
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *------------------------------------------------------------------
18 #ifndef _RDMA_MLX5DV_H_
19 #define _RDMA_MLX5DV_H_
22 #include <infiniband/mlx5dv.h>
23 #define always_inline static_always_inline
24 #include <vppinfra/types.h>
25 #include <vppinfra/error.h>
26 /* CQE flags - bits 16-31 of qword at offset 0x1c */
27 #define CQE_FLAG_L4_OK (1 << 10)
28 #define CQE_FLAG_L3_OK (1 << 9)
29 #define CQE_FLAG_L2_OK (1 << 8)
30 #define CQE_FLAG_IP_FRAG (1 << 7)
31 #define CQE_FLAG_L4_HDR_TYPE(f) (((f) >> 4) & 7)
32 #define CQE_FLAG_L3_HDR_TYPE_SHIFT (2)
33 #define CQE_FLAG_L3_HDR_TYPE_MASK (3 << CQE_FLAG_L3_HDR_TYPE_SHIFT)
34 #define CQE_FLAG_L3_HDR_TYPE(f) (((f) & CQE_FLAG_L3_HDR_TYPE_MASK) >> CQE_FLAG_L3_HDR_TYPE_SHIFT)
35 #define CQE_FLAG_L3_HDR_TYPE_IP4 2
36 #define CQE_FLAG_L3_HDR_TYPE_IP6 1
37 #define CQE_FLAG_IP_EXT_OPTS 1
39 /* CQE byte count (Striding RQ) */
40 #define CQE_BC_FILLER_MASK (1 << 31)
41 #define CQE_BC_CONSUMED_STRIDES_SHIFT (16)
42 #define CQE_BC_CONSUMED_STRIDES_MASK (0x3fff << CQE_BC_CONSUMED_STRIDES_SHIFT)
43 #define CQE_BC_BYTE_COUNT_MASK (0xffff)
59 u8 opcode_cqefmt_se_owner;
63 STATIC_ASSERT_SIZEOF (mlx5dv_cqe_t, 64);
79 } mlx5dv_wqe_ds_t; /* a WQE data segment */
87 } mlx5dv_wqe_srq_next_t;
89 #define foreach_cqe_rx_field \
90 _(0x1c, 26, 26, l4_ok) \
91 _(0x1c, 25, 25, l3_ok) \
92 _(0x1c, 24, 24, l2_ok) \
93 _(0x1c, 23, 23, ip_frag) \
94 _(0x1c, 22, 20, l4_hdr_type) \
95 _(0x1c, 19, 18, l3_hdr_type) \
96 _(0x1c, 17, 17, ip_ext_opts) \
98 _(0x2c, 31, 0, byte_cnt) \
99 _(0x30, 63, 0, timestamp) \
100 _(0x38, 31, 24, rx_drop_counter) \
101 _(0x38, 23, 0, flow_tag) \
102 _(0x3c, 31, 16, wqe_counter) \
103 _(0x3c, 15, 8, signature) \
104 _(0x3c, 7, 4, opcode) \
105 _(0x3c, 3, 2, cqe_format) \
110 /* inline functions */
113 mlx5_get_u32 (void *start, int offset)
115 return clib_net_to_host_u32 (*(u32 *) (((u8 *) start) + offset));
119 mlx5_get_u64 (void *start, int offset)
121 return clib_net_to_host_u64 (*(u64 *) (((u8 *) start) + offset));
125 mlx5_set_u32 (void *start, int offset, u32 value)
127 (*(u32 *) (((u8 *) start) + offset)) = clib_host_to_net_u32 (value);
131 mlx5_set_u64 (void *start, int offset, u64 value)
133 (*(u64 *) (((u8 *) start) + offset)) = clib_host_to_net_u64 (value);
137 mlx5_set_bits (void *start, int offset, int first, int last, u32 value)
139 u32 mask = (1 << (first - last + 1)) - 1;
140 u32 old = mlx5_get_u32 (start, offset);
141 if ((last == 0) && (first == 31))
143 mlx5_set_u32 (start, offset, value);
146 ASSERT (value == (value & mask));
148 old &= ~(mask << last);
149 mlx5_set_u32 (start, offset, old | value << last);
153 mlx5_get_bits (void *start, int offset, int first, int last)
155 u32 value = mlx5_get_u32 (start, offset);
156 if ((last == 0) && (first == 31))
159 value &= (1 << (first - last + 1)) - 1;
164 #endif /* RDMA_MLX5DV_H */
167 * fd.io coding-style-patch-verification: ON
170 * eval: (c-set-style "gnu")