2 * Copyright (c) 2018 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #ifndef __included_vmnet_vmnet_h__
17 #define __included_vmnet_vmnet_h__
19 #define foreach_vmxnet3_tx_func_error \
20 _(ERROR_PACKETS, "error packets") \
21 _(LINK_DOWN, "link down") \
22 _(NO_FREE_SLOTS, "no free tx slots")
26 #define _(f,s) VMXNET3_TX_ERROR_##f,
27 foreach_vmxnet3_tx_func_error
30 } vmxnet3_tx_func_error_t;
32 #define foreach_vmxnet3_rxmode_flags \
33 _(0, UCAST, "unicast") \
34 _(1, MCAST, "multicast") \
35 _(2, BCAST, "broadcast") \
36 _(3, ALL_MULTI, "all multicast") \
37 _(4, PROMISC, "promiscuous")
41 #define _(a, b, c) VMXNET3_RXMODE_##b = (1 << a),
42 foreach_vmxnet3_rxmode_flags
46 #define foreach_vmxnet3_show_entry \
47 _(RX_COMP, "rx comp") \
48 _(RX_DESC0, "rx desc 0") \
49 _(RX_DESC1, "rx desc 1") \
50 _(TX_COMP, "tx comp") \
55 #define _(a, b) VMXNET3_SHOW_##a,
56 foreach_vmxnet3_show_entry
60 #define foreach_vmxnet3_feature_flags \
61 _(0, RXCSUM, "rx checksum") \
63 _(2, RXVLAN, "rx VLAN") \
68 #define _(a, b, c) VMXNET3_F_##b = (1 << a),
69 foreach_vmxnet3_feature_flags
73 #define VMXNET3_TXQ_MAX 8
74 #define VMXNET3_TX_START(vd) ((vd)->queues)
75 #define VMXNET3_RX_START(vd) \
76 ((vd)->queues + (vd)->num_tx_queues * sizeof (vmxnet3_tx_queue))
79 #define VMXNET3_REG_IMR 0x0000 /* Interrupt Mask Register */
80 #define VMXNET3_REG_TXPROD 0x0600 /* Tx Producer Index */
81 #define VMXNET3_REG_RXPROD 0x0800 /* Rx Producer Index for ring 1 */
82 #define VMXNET3_REG_RXPROD2 0x0A00 /* Rx Producer Index for ring 2 */
86 #define VMXNET3_REG_VRRS 0x0000 /* VMXNET3 Revision Report Selection */
87 #define VMXNET3_REG_UVRS 0x0008 /* UPT Version Report Selection */
88 #define VMXNET3_REG_DSAL 0x0010 /* Driver Shared Address Low */
89 #define VMXNET3_REG_DSAH 0x0018 /* Driver Shared Address High */
90 #define VMXNET3_REG_CMD 0x0020 /* Command */
91 #define VMXNET3_REG_MACL 0x0028 /* MAC Address Low */
92 #define VMXNET3_REG_MACH 0x0030 /* MAC Address High */
93 #define VMXNET3_REG_ICR 0x0038 /* Interrupt Cause Register */
94 #define VMXNET3_REG_ECR 0x0040 /* Event Cause Register */
96 #define VMXNET3_VLAN_LEN 4
97 #define VMXNET3_FCS_LEN 4
98 #define VMXNET3_MTU (1514 + VMXNET3_VLAN_LEN + VMXNET3_FCS_LEN)
100 #define VMXNET3_RXF_BTYPE (1 << 14) /* rx body buffer type */
101 #define VMXNET3_RXF_GEN (1 << 31) /* rx generation */
103 #define VMXNET3_RXCF_CKSUM_MASK (0xFFFF) /* rx checksum mask */
104 #define VMXNET3_RXCF_TUC (1 << 16) /* rx udp/tcp checksum correct */
105 #define VMXNET3_RXCF_UDP (1 << 17) /* rx udp packet */
106 #define VMXNET3_RXCF_TCP (1 << 18) /* rx tcp packet */
107 #define VMXNET3_RXCF_IPC (1 << 19) /* rx ip checksum correct */
108 #define VMXNET3_RXCF_IP6 (1 << 20) /* rx ip6 packet */
109 #define VMXNET3_RXCF_IP4 (1 << 21) /* rx ip4 packet */
110 #define VMXNET3_RXCF_CT (0x7F << 24) /* rx completion type 24-30, 7 bits */
111 #define VMXNET3_RXCF_GEN (1 << 31) /* rx completion generation */
113 #define VMXNET3_RXC_INDEX (0xFFF) /* rx completion index mask */
115 #define foreach_vmxnet3_offload \
117 _(2, CSUM, "checksum") \
122 #define _(a, b, c) VMXNET3_OM_##b = (a),
123 foreach_vmxnet3_offload
128 #define VMXNET3_TXF_GEN (1 << 14) /* tx generation */
131 #define VMXNET3_TXF_OM(x) ((x) << 10) /* tx offload mode */
132 #define VMXNET3_TXF_MSSCOF(x) ((x) << 18) /* tx MSS checksum offset, flags */
133 #define VMXNET3_TXF_EOP (1 << 12) /* tx end of packet */
134 #define VMXNET3_TXF_CQ (1 << 13) /* tx completion request */
136 /* tx completion flag */
137 #define VMXNET3_TXCF_GEN (1 << 31) /* tx completion generation */
138 #define VMXNET3_TXC_INDEX (0xFFF) /* tx completion index mask */
140 #define VMXNET3_RX_RING_SIZE 2
141 #define VMXNET3_INPUT_REFILL_THRESHOLD 32
142 #define VMXNET3_NUM_TX_DESC 1024
143 #define VMXNET3_NUM_TX_COMP VMXNET3_NUM_TX_DESC
144 #define VMXNET3_NUM_RX_DESC 1024
145 #define VMXNET3_NUM_RX_COMP VMXNET3_NUM_RX_DESC
147 #define VMXNET3_VERSION_MAGIC 0x69505845
148 #define VMXNET3_SHARED_MAGIC 0xbabefee1
149 #define VMXNET3_VERSION_SELECT 1
150 #define VMXNET3_UPT_VERSION_SELECT 1
151 #define VMXNET3_MAX_INTRS 25
152 #define VMXNET3_IC_DISABLE_ALL 0x1
154 #define VMXNET3_GOS_BITS_32 (1 << 0)
155 #define VMXNET3_GOS_BITS_64 (2 << 0)
156 #define VMXNET3_GOS_TYPE_LINUX (1 << 2)
157 #define VMXNET3_RXCL_LEN_MASK (0x3FFF) // 14 bits
158 #define VMXNET3_RXCL_ERROR (1 << 14)
160 #define VMXNET3_RXCI_EOP (1 << 14) /* end of packet */
161 #define VMXNET3_RXCI_SOP (1 << 15) /* start of packet */
162 #define VMXNET3_RXCI_CNC (1 << 30) /* Checksum not calculated */
164 #define VMXNET3_RXCOMP_TYPE (3 << 24) /* RX completion descriptor */
165 #define VMXNET3_RXCOMP_TYPE_LRO (4 << 24) /* RX completion descriptor for LRO */
167 #define VMXNET3_RXECF_MSS_MASK (0xFFFF) // 16 bits
169 #define foreach_vmxnet3_device_flags \
170 _(0, INITIALIZED, "initialized") \
171 _(1, ERROR, "error") \
172 _(2, ADMIN_UP, "admin-up") \
174 _(4, LINK_UP, "link-up") \
175 _(5, SHARED_TXQ_LOCK, "shared-txq-lock") \
180 #define _(a, b, c) VMXNET3_DEVICE_F_##b = (1 << a),
181 foreach_vmxnet3_device_flags
185 #define foreach_vmxnet3_set_cmds \
186 _(0, ACTIVATE_DEV, "activate device") \
187 _(1, QUIESCE_DEV, "quiesce device") \
188 _(2, RESET_DEV, "reset device") \
189 _(3, UPDATE_RX_MODE, "update rx mode") \
190 _(4, UPDATE_MAC_FILTERS, "update mac filters") \
191 _(5, UPDATE_VLAN_FILTERS, "update vlan filters") \
192 _(6, UPDATE_RSSIDT, "update rss idt") \
193 _(7, UPDATE_IML, "update iml") \
194 _(8, UPDATE_PMCFG, "update pm cfg") \
195 _(9, UPDATE_FEATURE, "update feature") \
196 _(10, STOP_EMULATION, "stop emulation") \
197 _(11, LOAD_PLUGIN, "load plugin") \
198 _(12, ACTIVATE_VF, "activate vf") \
199 _(13, RESERVED3, "reserved 3") \
200 _(14, RESERVED4, "reservced 4") \
201 _(15, REGISTER_MEMREGS, "register mem regs")
205 #define _(a, b, c) VMXNET3_CMD_##b = (a + 0xCAFE0000),
206 foreach_vmxnet3_set_cmds
210 #define foreach_vmxnet3_get_cmds \
211 _(0, GET_QUEUE_STATUS, "get queue status") \
212 _(1, GET_STATS, "get stats") \
213 _(2, GET_LINK, "get link") \
214 _(3, GET_PERM_MAC_LO, "get perm mac lo") \
215 _(4, GET_PERM_MAC_HI, "get perm mac hi") \
216 _(5, GET_DID_LO, "get did lo") \
217 _(6, GET_DID_HI, "get did hi") \
218 _(7, GET_DEV_EXTRA_INFO, "get dev extra info") \
219 _(8, GET_CONF_INTR, "get conf intr") \
220 _(9, GET_ADAPTIVE_RING_INFO, "get adaptive ring info") \
221 _(10, GET_TXDATA_DESC_SIZE, "get txdata desc size") \
222 _(11, RESERVED5, "reserved5")
226 #define _(a, b, c) VMXNET3_CMD_##b = (a + 0xF00D0000),
227 foreach_vmxnet3_get_cmds
231 typedef CLIB_PACKED (struct
233 u32 version; u32 guest_info; u32 version_support;
234 u32 upt_version_support; u64 upt_features;
235 u64 driver_data_address; u64 queue_desc_address;
236 u32 driver_data_len; u32 queue_desc_len;
238 u16 max_num_rx_sg; u8 num_tx_queues; u8 num_rx_queues;
240 }) vmxnet3_misc_config;
242 typedef CLIB_PACKED (struct
247 u8 moderation_level[VMXNET3_MAX_INTRS]; u32 control;
249 }) vmxnet3_interrupt_config;
251 typedef CLIB_PACKED (struct
253 u32 mode; u16 multicast_len; u16 pad;
254 u64 multicast_address; u8 vlan_filter[512];
255 }) vmxnet3_rx_filter_config;
257 typedef CLIB_PACKED (struct
259 u32 version; u32 length;
261 }) vmxnet3_variable_config;
263 typedef CLIB_PACKED (struct
267 vmxnet3_misc_config misc;
268 vmxnet3_interrupt_config interrupt;
269 vmxnet3_rx_filter_config rx_filter;
270 vmxnet3_variable_config rss;
271 vmxnet3_variable_config pattern;
272 vmxnet3_variable_config plugin; u32 ecr;
276 typedef CLIB_PACKED (struct
281 }) vmxnet3_queue_status;
283 typedef CLIB_PACKED (struct
285 u32 num_deferred; u32 threshold;
287 }) vmxnet3_tx_queue_control;
289 typedef CLIB_PACKED (struct
293 u64 comp_address; u64 driver_data_address; u64 pad;
295 u32 num_data; u32 num_comp; u32 driver_data_len;
297 u8 pad1; u16 data_address_size; u8 pad2[4];
298 }) vmxnet3_tx_queue_config;
300 typedef CLIB_PACKED (struct
304 u64 ucast_pkts; u64 ucast_bytes; u64 mcast_pkts;
306 u64 bcast_pkts; u64 bcast_bytes; u64 error_pkts;
310 typedef CLIB_PACKED (struct
312 vmxnet3_tx_queue_control ctrl;
313 vmxnet3_tx_queue_config cfg;
314 vmxnet3_queue_status status; vmxnet3_tx_stats stats;
318 typedef CLIB_PACKED (struct
320 u8 update_prod; u8 pad[7];
322 }) vmxnet3_rx_queue_control;
324 typedef CLIB_PACKED (struct
327 u64 comp_address; u64 driver_data_address;
328 u64 data_address; u32 num_desc[2];
330 u32 driver_data_len; u8 intr_index; u8 pad1;
331 u16 data_address_size; u8 pad2[4];
332 }) vmxnet3_rx_queue_config;
334 typedef CLIB_PACKED (struct
338 u64 ucast_pkts; u64 ucast_bytes; u64 mcast_pkts;
340 u64 bcast_pkts; u64 bcast_bytes; u64 nobuf_pkts;
344 typedef CLIB_PACKED (struct
346 vmxnet3_rx_queue_control ctrl;
347 vmxnet3_rx_queue_config cfg;
348 vmxnet3_queue_status status; vmxnet3_rx_stats stats;
354 * buffer length -- bits 0-13
355 * buffer type -- bit 14
356 * descriptor type -- bit 15
357 * reserved -- bits 16-30
358 * generation -- bit 31
360 typedef CLIB_PACKED (struct
369 * RX desc index -- bits 0-11
371 * end of packet -- bit 14
372 * start of packet -- bit 15
373 * ring ID -- bits 16-25
374 * RSS hash type -- bits 26-29
375 * checksum not calculated -- bit 30
378 * rss: RSS hash value
381 * data length -- bits 0-13
383 * tag is stripped -- bit 15
384 * tag stripped -- bits 16-31
387 * checksum -- bits 0 - 15
388 * tcp/udp checksum correct-- bit 16
389 * udp packet -- bit 17
390 * tcp packet -- bit 18
391 * ip checksum correct -- bit 19
394 * ip fragment -- bit 22
395 * frame crc correct -- bit 23
396 * completion type -- bits 24-30
397 * generation -- bit 31
399 typedef CLIB_PACKED (struct
409 * tcp/udp checksum correct-- bit 16
410 * udp packet -- bit 17
411 * tcp packet -- bit 18
412 * ip checksum correct -- bit 19
415 * ip fragment -- bit 22
416 * frame crc correct -- bit 23
417 * completion type -- bits 24-30
418 * generation -- bit 31
420 typedef CLIB_PACKED (struct
423 u8 seg_cnt; u8 dup_ack_cnt; u16 ts_delta; u32 dword2;
425 }) vmxnet3_rx_comp_ext;
429 * TX desc index -- bits 0-11
433 * reserved -- bits 0-23
434 * completion type -- bits 24-30
435 * generation -- bit 31
437 typedef CLIB_PACKED (struct
446 * length -- bits 0-13
447 * generation -- bit 14
449 * descriptor type -- bit 16
451 * MSS, checksum offset -- bits 18-31
453 * header length -- bits 0-9
454 * offload mode -- bits 10-11
455 * end of packet -- bit 12
456 * completion request -- bit 13
458 * vlan tag insertion -- bit 15
459 * tag to insert -- bits 16-31
461 typedef CLIB_PACKED (struct
469 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
480 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
483 } vmxnet3_rx_comp_ring;
487 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
490 vmxnet3_rx_ring rx_ring[VMXNET3_RX_RING_SIZE];
491 vmxnet3_rx_desc *rx_desc[VMXNET3_RX_RING_SIZE];
492 vmxnet3_rx_comp *rx_comp;
493 vmxnet3_rx_comp_ring rx_comp_ring;
498 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
507 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
510 } vmxnet3_tx_comp_ring;
514 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
517 clib_spinlock_t lock;
519 vmxnet3_tx_desc *tx_desc;
520 vmxnet3_tx_comp *tx_comp;
521 vmxnet3_tx_ring tx_ring;
522 vmxnet3_tx_comp_ring tx_comp_ring;
527 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
529 u32 per_interface_next_index;
535 vlib_pci_dev_handle_t pci_dev_handle;
536 vlib_pci_addr_t pci_addr;
553 vmxnet3_shared *driver_shared;
558 vmxnet3_tx_stats *tx_stats;
559 vmxnet3_rx_stats *rx_stats;
564 vmxnet3_device_t *devices;
566 vlib_log_class_t log_default;
570 extern vmxnet3_main_t vmxnet3_main;
574 vlib_pci_addr_t addr;
583 } vmxnet3_create_if_args_t;
589 vlib_buffer_t buffer;
590 } vmxnet3_input_trace_t;
592 void vmxnet3_create_if (vlib_main_t * vm, vmxnet3_create_if_args_t * args);
593 void vmxnet3_delete_if (vlib_main_t * vm, vmxnet3_device_t * ad);
595 extern clib_error_t *vmxnet3_plugin_api_hookup (vlib_main_t * vm);
596 extern vlib_node_registration_t vmxnet3_input_node;
597 extern vnet_device_class_t vmxnet3_device_class;
600 format_function_t format_vmxnet3_device;
601 format_function_t format_vmxnet3_device_name;
602 format_function_t format_vmxnet3_input_trace;
604 #define vmxnet3_log_debug(dev, f, ...) \
605 vlib_log (VLIB_LOG_LEVEL_DEBUG, vmxnet3_main.log_default, "%U: " f, \
606 format_vlib_pci_addr, &dev->pci_addr, \
609 #define vmxnet3_log_error(dev, f, ...) \
610 vlib_log (VLIB_LOG_LEVEL_ERR, vmxnet3_main.log_default, "%U: " f, \
611 format_vlib_pci_addr, &dev->pci_addr, \
614 /* no log version, called by data plane */
615 static_always_inline void
616 vmxnet3_reg_write_inline (vmxnet3_device_t * vd, u8 bar, u32 addr, u32 val)
618 *(volatile u32 *) ((u8 *) vd->bar[bar] + addr) = val;
621 static_always_inline void
622 vmxnet3_reg_write (vmxnet3_device_t * vd, u8 bar, u32 addr, u32 val)
624 vmxnet3_log_debug (vd, "reg wr bar %u addr 0x%x val 0x%x", bar, addr, val);
625 vmxnet3_reg_write_inline (vd, bar, addr, val);
628 static_always_inline u32
629 vmxnet3_reg_read (vmxnet3_device_t * vd, u8 bar, u32 addr)
633 val = *(volatile u32 *) (vd->bar[bar] + addr);
634 vmxnet3_log_debug (vd, "reg rd bar %u addr 0x%x val 0x%x", bar, addr, val);
639 static_always_inline uword
640 vmxnet3_dma_addr (vlib_main_t * vm, vmxnet3_device_t * vd, void *p)
642 return (vd->flags & VMXNET3_DEVICE_F_IOVA) ? pointer_to_uword (p) :
643 vlib_physmem_get_pa (vm, p);
646 static_always_inline void
647 vmxnet3_rx_ring_advance_produce (vmxnet3_rxq_t * rxq, vmxnet3_rx_ring * ring)
650 if (PREDICT_FALSE (ring->produce == rxq->size))
653 ring->gen ^= VMXNET3_RXF_GEN;
657 static_always_inline clib_error_t *
658 vmxnet3_rxq_refill_ring0 (vlib_main_t * vm, vmxnet3_device_t * vd,
661 vmxnet3_rx_desc *rxd;
662 u16 n_refill, n_alloc;
663 vmxnet3_rx_ring *ring;
664 vmxnet3_rx_queue *rx;
666 ring = &rxq->rx_ring[0];
667 n_refill = rxq->size - ring->fill;
669 if (PREDICT_TRUE (n_refill <= VMXNET3_INPUT_REFILL_THRESHOLD))
673 vlib_buffer_alloc_to_ring (vm, ring->bufs, ring->produce, rxq->size,
675 if (PREDICT_FALSE (n_alloc != n_refill))
678 vlib_buffer_free_from_ring (vm, ring->bufs, ring->produce, rxq->size,
680 return clib_error_return (0, "buffer alloc failed");
685 vlib_buffer_t *b = vlib_get_buffer (vm, ring->bufs[ring->produce]);
686 rxd = &rxq->rx_desc[0][ring->produce];
687 rxd->address = vlib_buffer_get_pa (vm, b);
688 rxd->flags = ring->gen | vlib_buffer_get_default_data_size (vm);
690 vmxnet3_rx_ring_advance_produce (rxq, ring);
695 rx = VMXNET3_RX_START (vd);
696 if (PREDICT_FALSE (rx->ctrl.update_prod))
697 vmxnet3_reg_write_inline (vd, 0, VMXNET3_REG_RXPROD, ring->produce);
702 static_always_inline clib_error_t *
703 vmxnet3_rxq_refill_ring1 (vlib_main_t * vm, vmxnet3_device_t * vd,
706 vmxnet3_rx_desc *rxd;
707 u16 n_refill, n_alloc;
708 vmxnet3_rx_ring *ring;
709 vmxnet3_rx_queue *rx;
711 ring = &rxq->rx_ring[1];
712 n_refill = rxq->size - ring->fill;
714 if (PREDICT_TRUE (n_refill <= VMXNET3_INPUT_REFILL_THRESHOLD))
718 vlib_buffer_alloc_to_ring (vm, ring->bufs, ring->produce, rxq->size,
720 if (PREDICT_FALSE (n_alloc != n_refill))
723 vlib_buffer_free_from_ring (vm, ring->bufs, ring->produce, rxq->size,
725 return clib_error_return (0, "buffer alloc failed");
730 vlib_buffer_t *b = vlib_get_buffer (vm, ring->bufs[ring->produce]);
731 rxd = &rxq->rx_desc[1][ring->produce];
732 rxd->address = vlib_buffer_get_pa (vm, b);
733 rxd->flags = ring->gen | vlib_buffer_get_default_data_size (vm) |
736 vmxnet3_rx_ring_advance_produce (rxq, ring);
741 rx = VMXNET3_RX_START (vd);
742 if (PREDICT_FALSE (rx->ctrl.update_prod))
743 vmxnet3_reg_write_inline (vd, 0, VMXNET3_REG_RXPROD2, ring->produce);
748 #endif /* __included_vmnet_vmnet_h__ */
750 * fd.io coding-style-patch-verification: ON
753 * eval: (c-set-style "gnu")