2 * Copyright (c) 2018 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #ifndef __included_vmnet_vmnet_h__
17 #define __included_vmnet_vmnet_h__
19 #define foreach_vmxnet3_tx_func_error \
20 _(ERROR_PACKETS, "error packets") \
21 _(LINK_DOWN, "link down") \
22 _(NO_FREE_SLOTS, "no free tx slots")
26 #define _(f,s) VMXNET3_TX_ERROR_##f,
27 foreach_vmxnet3_tx_func_error
30 } vmxnet3_tx_func_error_t;
32 #define foreach_vmxnet3_rxmode_flags \
33 _(0, UCAST, "unicast") \
34 _(1, MCAST, "multicast") \
35 _(2, BCAST, "broadcast") \
36 _(3, ALL_MULTI, "all multicast") \
37 _(4, PROMISC, "promiscuous")
41 #define _(a, b, c) VMXNET3_RXMODE_##b = (1 << a),
42 foreach_vmxnet3_rxmode_flags
46 #define foreach_vmxnet3_show_entry \
47 _(RX_COMP, "rx comp") \
48 _(RX_DESC0, "rx desc 0") \
49 _(RX_DESC1, "rx desc 1") \
50 _(TX_COMP, "tx comp") \
55 #define _(a, b) VMXNET3_SHOW_##a,
56 foreach_vmxnet3_show_entry
61 #define VMXNET3_REG_IMR 0x0000 /* Interrupt Mask Register */
62 #define VMXNET3_REG_TXPROD 0x0600 /* Tx Producer Index */
63 #define VMXNET3_REG_RXPROD 0x0800 /* Rx Producer Index for ring 1 */
64 #define VMXNET3_REG_RXPROD2 0x0A00 /* Rx Producer Index for ring 2 */
68 #define VMXNET3_REG_VRRS 0x0000 /* VMXNET3 Revision Report Selection */
69 #define VMXNET3_REG_UVRS 0x0008 /* UPT Version Report Selection */
70 #define VMXNET3_REG_DSAL 0x0010 /* Driver Shared Address Low */
71 #define VMXNET3_REG_DSAH 0x0018 /* Driver Shared Address High */
72 #define VMXNET3_REG_CMD 0x0020 /* Command */
73 #define VMXNET3_REG_MACL 0x0028 /* MAC Address Low */
74 #define VMXNET3_REG_MACH 0x0030 /* MAC Address High */
75 #define VMXNET3_REG_ICR 0x0038 /* Interrupt Cause Register */
76 #define VMXNET3_REG_ECR 0x0040 /* Event Cause Register */
78 #define VMXNET3_VLAN_LEN 4
79 #define VMXNET3_FCS_LEN 4
80 #define VMXNET3_MTU (1514 + VMXNET3_VLAN_LEN + VMXNET3_FCS_LEN)
82 #define VMXNET3_RXF_BTYPE (1 << 14) /* rx body buffer type */
83 #define VMXNET3_RXF_GEN (1 << 31) /* rx generation */
84 #define VMXNET3_RXCF_IP6 (1 << 20) /* rx ip6 packet */
85 #define VMXNET3_RXCF_IP4 (1 << 21) /* rx ip4 packet */
86 #define VMXNET3_RXCF_GEN (1 << 31) /* rx completion generation */
87 #define VMXNET3_RXC_INDEX (0xFFF) /* rx completion index mask */
89 #define VMXNET3_TXF_GEN (1 << 14) /* tx generation */
90 #define VMXNET3_TXF_EOP (1 << 12) /* tx end of packet */
91 #define VMXNET3_TXF_CQ (1 << 13) /* tx completion request */
92 #define VMXNET3_TXCF_GEN (1 << 31) /* tx completion generation */
93 #define VMXNET3_TXC_INDEX (0xFFF) /* tx completion index mask */
95 #define VMXNET3_RX_RING_SIZE 2
96 #define VMXNET3_INPUT_REFILL_THRESHOLD 32
97 #define VMXNET3_NUM_TX_DESC 1024
98 #define VMXNET3_NUM_TX_COMP VMXNET3_NUM_TX_DESC
99 #define VMXNET3_NUM_RX_DESC 1024
100 #define VMXNET3_NUM_RX_COMP VMXNET3_NUM_RX_DESC
102 #define VMXNET3_VERSION_MAGIC 0x69505845
103 #define VMXNET3_SHARED_MAGIC 0xbabefee1
104 #define VMXNET3_VERSION_SELECT 1
105 #define VMXNET3_UPT_VERSION_SELECT 1
106 #define VMXNET3_MAX_INTRS 25
107 #define VMXNET3_IC_DISABLE_ALL 0x1
109 #define VMXNET3_GOS_BITS_32 (1 << 0)
110 #define VMXNET3_GOS_BITS_64 (2 << 0)
111 #define VMXNET3_GOS_TYPE_LINUX (1 << 2)
112 #define VMXNET3_RXCL_LEN_MASK (0x3FFF) // 14 bits
113 #define VMXNET3_RXCL_ERROR (1 << 14)
114 #define VMXNET3_RXCI_EOP (1 << 14)
115 #define VMXNET3_RXCI_SOP (1 << 15)
117 #define foreach_vmxnet3_device_flags \
118 _(0, INITIALIZED, "initialized") \
119 _(1, ERROR, "error") \
120 _(2, ADMIN_UP, "admin-up") \
122 _(4, LINK_UP, "link-up") \
123 _(5, SHARED_TXQ_LOCK, "shared-txq-lock") \
128 #define _(a, b, c) VMXNET3_DEVICE_F_##b = (1 << a),
129 foreach_vmxnet3_device_flags
133 #define foreach_vmxnet3_set_cmds \
134 _(0, ACTIVATE_DEV, "activate device") \
135 _(1, QUIESCE_DEV, "quiesce device") \
136 _(2, RESET_DEV, "reset device") \
137 _(3, UPDATE_RX_MODE, "update rx mode") \
138 _(4, UPDATE_MAC_FILTERS, "update mac filters") \
139 _(5, UPDATE_VLAN_FILTERS, "update vlan filters") \
140 _(6, UPDATE_RSSIDT, "update rss idt") \
141 _(7, UPDATE_IML, "update iml") \
142 _(8, UPDATE_PMCFG, "update pm cfg") \
143 _(9, UPDATE_FEATURE, "update feature") \
144 _(10, STOP_EMULATION, "stop emulation") \
145 _(11, LOAD_PLUGIN, "load plugin") \
146 _(12, ACTIVATE_VF, "activate vf") \
147 _(13, RESERVED3, "reserved 3") \
148 _(14, RESERVED4, "reservced 4") \
149 _(15, REGISTER_MEMREGS, "register mem regs")
153 #define _(a, b, c) VMXNET3_CMD_##b = (a + 0xCAFE0000),
154 foreach_vmxnet3_set_cmds
158 #define foreach_vmxnet3_get_cmds \
159 _(0, GET_QUEUE_STATUS, "get queue status") \
160 _(1, GET_STATS, "get stats") \
161 _(2, GET_LINK, "get link") \
162 _(3, GET_PERM_MAC_LO, "get perm mac lo") \
163 _(4, GET_PERM_MAC_HI, "get perm mac hi") \
164 _(5, GET_DID_LO, "get did lo") \
165 _(6, GET_DID_HI, "get did hi") \
166 _(7, GET_DEV_EXTRA_INFO, "get dev extra info") \
167 _(8, GET_CONF_INTR, "get conf intr") \
168 _(9, GET_ADAPTIVE_RING_INFO, "get adaptive ring info") \
169 _(10, GET_TXDATA_DESC_SIZE, "get txdata desc size") \
170 _(11, RESERVED5, "reserved5")
174 #define _(a, b, c) VMXNET3_CMD_##b = (a + 0xF00D0000),
175 foreach_vmxnet3_get_cmds
179 typedef CLIB_PACKED (struct
181 u32 version; u32 guest_info; u32 version_support;
182 u32 upt_version_support; u64 upt_features;
183 u64 driver_data_address; u64 queue_desc_address;
184 u32 driver_data_len; u32 queue_desc_len;
186 u16 max_num_rx_sg; u8 num_tx_queues; u8 num_rx_queues;
188 }) vmxnet3_misc_config;
190 typedef CLIB_PACKED (struct
195 u8 moderation_level[VMXNET3_MAX_INTRS]; u32 control;
197 }) vmxnet3_interrupt_config;
199 typedef CLIB_PACKED (struct
203 u16 pad; u64 multicast_address; u8 vlan_filter[512];
204 }) vmxnet3_rx_filter_config;
206 typedef CLIB_PACKED (struct
208 u32 version; u32 length;
210 }) vmxnet3_variable_config;
212 typedef CLIB_PACKED (struct
216 vmxnet3_misc_config misc;
217 vmxnet3_interrupt_config interrupt;
218 vmxnet3_rx_filter_config rx_filter;
219 vmxnet3_variable_config rss;
220 vmxnet3_variable_config pattern;
221 vmxnet3_variable_config plugin; u32 ecr;
225 typedef CLIB_PACKED (struct
230 }) vmxnet3_queue_status;
232 typedef CLIB_PACKED (struct
234 u32 num_deferred; u32 threshold;
236 }) vmxnet3_tx_queue_control;
238 typedef CLIB_PACKED (struct
242 u64 comp_address; u64 driver_data_address; u64 pad;
245 u32 num_comp; u32 driver_data_len; u8 intr_index;
247 }) vmxnet3_tx_queue_config;
249 typedef CLIB_PACKED (struct
253 u64 ucast_pkts; u64 ucast_bytes; u64 mcast_pkts;
255 u64 bcast_pkts; u64 bcast_bytes; u64 error_pkts;
259 typedef CLIB_PACKED (struct
261 vmxnet3_tx_queue_control ctrl;
262 vmxnet3_tx_queue_config cfg;
263 vmxnet3_queue_status status; vmxnet3_tx_stats stats;
267 typedef CLIB_PACKED (struct
269 u8 update_prod; u8 pad[7];
271 }) vmxnet3_rx_queue_control;
273 typedef CLIB_PACKED (struct
276 u64 comp_address; u64 driver_data_address; u64 pad;
278 u32 num_comp; u32 driver_data_len; u8 intr_index;
280 }) vmxnet3_rx_queue_config;
282 typedef CLIB_PACKED (struct
286 u64 ucast_pkts; u64 ucast_bytes; u64 mcast_pkts;
288 u64 bcast_pkts; u64 bcast_bytes; u64 nobuf_pkts;
292 typedef CLIB_PACKED (struct
294 vmxnet3_rx_queue_control ctrl;
295 vmxnet3_rx_queue_config cfg;
296 vmxnet3_queue_status status; vmxnet3_rx_stats stats;
300 typedef CLIB_PACKED (struct
302 vmxnet3_tx_queue tx; vmxnet3_rx_queue rx;
307 * buffer length -- bits 0-13
308 * buffer type -- bit 14
309 * descriptor type -- bit 15
310 * reserved -- bits 16-30
311 * generation -- bit 31
313 typedef CLIB_PACKED (struct
322 * RX desc index -- bits 0-11
324 * end of packet -- bit 14
325 * start of packet -- bit 15
326 * ring ID -- bits 16-25
327 * RSS hash type -- bits 26-29
328 * checksum not calculated -- bit 30
331 * rss: RSS hash value
334 * data length -- bits 0-13
336 * tag is stripped -- bit 15
337 * tag stripped -- bits 16-31
340 * checksum -- bits 0 - 15
341 * tcp/udp checksum correct-- bit 16
342 * udp packet -- bit 17
343 * tcp packet -- bit 18
344 * ip checksum correct -- bit 19
347 * ip fragment -- bit 22
348 * frame crc correct -- bit 23
349 * completion type -- bits 24-30
350 * generation -- bit 31
352 typedef CLIB_PACKED (struct
361 * TX desc index -- bits 0-11
365 * reserved -- bits 0-23
366 * completion type -- bits 24-30
367 * generation -- bit 31
369 typedef CLIB_PACKED (struct
378 * length -- bits 0-13
379 * generation -- bit 14
381 * descriptor type -- bit 16
383 * MSS, checksum offset -- bits 18-31
385 * header length -- bits 0-9
386 * offload mode -- bits 10-11
387 * end of packet -- bit 12
388 * completion request -- bit 13
390 * vlan tag insertion -- bit 15
391 * tag to insert -- bits 16-31
393 typedef CLIB_PACKED (struct
401 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
412 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
415 } vmxnet3_rx_comp_ring;
419 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
422 vmxnet3_rx_ring rx_ring[VMXNET3_RX_RING_SIZE];
423 vmxnet3_rx_desc *rx_desc[VMXNET3_RX_RING_SIZE];
424 vmxnet3_rx_comp *rx_comp;
425 vmxnet3_rx_comp_ring rx_comp_ring;
430 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
439 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
442 } vmxnet3_tx_comp_ring;
446 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
448 clib_spinlock_t lock;
450 vmxnet3_tx_desc *tx_desc;
451 vmxnet3_tx_comp *tx_comp;
452 vmxnet3_tx_ring tx_ring;
453 vmxnet3_tx_comp_ring tx_comp_ring;
456 typedef CLIB_PACKED (struct
458 vmxnet3_queues queues; vmxnet3_shared shared;
463 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
465 u32 per_interface_next_index;
470 vlib_pci_dev_handle_t pci_dev_handle;
471 vlib_pci_addr_t pci_addr;
495 vmxnet3_device_t *devices;
497 vlib_log_class_t log_default;
500 extern vmxnet3_main_t vmxnet3_main;
504 vlib_pci_addr_t addr;
512 } vmxnet3_create_if_args_t;
518 vlib_buffer_t buffer;
519 } vmxnet3_input_trace_t;
521 void vmxnet3_create_if (vlib_main_t * vm, vmxnet3_create_if_args_t * args);
522 void vmxnet3_delete_if (vlib_main_t * vm, vmxnet3_device_t * ad);
524 extern clib_error_t *vmxnet3_plugin_api_hookup (vlib_main_t * vm);
525 extern vlib_node_registration_t vmxnet3_input_node;
526 extern vnet_device_class_t vmxnet3_device_class;
529 format_function_t format_vmxnet3_device;
530 format_function_t format_vmxnet3_device_name;
531 format_function_t format_vmxnet3_input_trace;
533 #define vmxnet3_log_debug(dev, f, ...) \
534 vlib_log (VLIB_LOG_LEVEL_DEBUG, vmxnet3_main.log_default, "%U: " f, \
535 format_vlib_pci_addr, &dev->pci_addr, \
538 #define vmxnet3_log_error(dev, f, ...) \
539 vlib_log (VLIB_LOG_LEVEL_ERR, vmxnet3_main.log_default, "%U: " f, \
540 format_vlib_pci_addr, &dev->pci_addr, \
543 /* no log version, called by data plane */
544 static_always_inline void
545 vmxnet3_reg_write_inline (vmxnet3_device_t * vd, u8 bar, u32 addr, u32 val)
547 *(volatile u32 *) ((u8 *) vd->bar[bar] + addr) = val;
550 static_always_inline void
551 vmxnet3_reg_write (vmxnet3_device_t * vd, u8 bar, u32 addr, u32 val)
553 vmxnet3_log_debug (vd, "reg wr bar %u addr 0x%x val 0x%x", bar, addr, val);
554 vmxnet3_reg_write_inline (vd, bar, addr, val);
557 static_always_inline u32
558 vmxnet3_reg_read (vmxnet3_device_t * vd, u8 bar, u32 addr)
562 val = *(volatile u32 *) (vd->bar[bar] + addr);
563 vmxnet3_log_debug (vd, "reg rd bar %u addr 0x%x val 0x%x", bar, addr, val);
568 static_always_inline uword
569 vmxnet3_dma_addr (vlib_main_t * vm, vmxnet3_device_t * vd, void *p)
571 return (vd->flags & VMXNET3_DEVICE_F_IOVA) ? pointer_to_uword (p) :
572 vlib_physmem_get_pa (vm, p);
575 static_always_inline void
576 vmxnet3_rx_ring_advance_produce (vmxnet3_rxq_t * rxq, vmxnet3_rx_ring * ring)
579 if (PREDICT_FALSE (ring->produce == rxq->size))
582 ring->gen ^= VMXNET3_RXF_GEN;
586 static_always_inline clib_error_t *
587 vmxnet3_rxq_refill_ring0 (vlib_main_t * vm, vmxnet3_device_t * vd,
590 vmxnet3_rx_desc *rxd;
591 u16 n_refill, n_alloc;
592 vmxnet3_rx_ring *ring;
595 ring = &rxq->rx_ring[0];
596 n_refill = rxq->size - ring->fill;
598 if (PREDICT_TRUE (n_refill <= VMXNET3_INPUT_REFILL_THRESHOLD))
602 vlib_buffer_alloc_to_ring (vm, ring->bufs, ring->produce, rxq->size,
604 if (PREDICT_FALSE (n_alloc != n_refill))
607 vlib_buffer_free_from_ring (vm, ring->bufs, ring->produce, rxq->size,
609 return clib_error_return (0, "buffer alloc failed");
614 vlib_buffer_t *b = vlib_get_buffer (vm, ring->bufs[ring->produce]);
615 rxd = &rxq->rx_desc[0][ring->produce];
616 rxd->address = vlib_buffer_get_pa (vm, b);
617 rxd->flags = ring->gen | VLIB_BUFFER_DATA_SIZE;
619 vmxnet3_rx_ring_advance_produce (rxq, ring);
624 q = &vd->dma->queues;
625 if (PREDICT_FALSE (q->rx.ctrl.update_prod))
626 vmxnet3_reg_write_inline (vd, 0, VMXNET3_REG_RXPROD, ring->produce);
631 static_always_inline clib_error_t *
632 vmxnet3_rxq_refill_ring1 (vlib_main_t * vm, vmxnet3_device_t * vd,
635 vmxnet3_rx_desc *rxd;
636 u16 n_refill, n_alloc;
637 vmxnet3_rx_ring *ring;
640 ring = &rxq->rx_ring[1];
641 n_refill = rxq->size - ring->fill;
643 if (PREDICT_TRUE (n_refill <= VMXNET3_INPUT_REFILL_THRESHOLD))
647 vlib_buffer_alloc_to_ring (vm, ring->bufs, ring->produce, rxq->size,
649 if (PREDICT_FALSE (n_alloc != n_refill))
652 vlib_buffer_free_from_ring (vm, ring->bufs, ring->produce, rxq->size,
654 return clib_error_return (0, "buffer alloc failed");
659 vlib_buffer_t *b = vlib_get_buffer (vm, ring->bufs[ring->produce]);
660 rxd = &rxq->rx_desc[1][ring->produce];
661 rxd->address = vlib_buffer_get_pa (vm, b);
662 rxd->flags = ring->gen | VLIB_BUFFER_DATA_SIZE | VMXNET3_RXF_BTYPE;
664 vmxnet3_rx_ring_advance_produce (rxq, ring);
669 q = &vd->dma->queues;
670 if (PREDICT_FALSE (q->rx.ctrl.update_prod))
671 vmxnet3_reg_write_inline (vd, 0, VMXNET3_REG_RXPROD2, ring->produce);
676 #endif /* __included_vmnet_vmnet_h__ */
678 * fd.io coding-style-patch-verification: ON
681 * eval: (c-set-style "gnu")