2 * Copyright (c) 2016 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 * pci.c: Linux user space PCI bus management.
18 * Copyright (c) 2008 Eliot Dresselhaus
20 * Permission is hereby granted, free of charge, to any person obtaining
21 * a copy of this software and associated documentation files (the
22 * "Software"), to deal in the Software without restriction, including
23 * without limitation the rights to use, copy, modify, merge, publish,
24 * distribute, sublicense, and/or sell copies of the Software, and to
25 * permit persons to whom the Software is furnished to do so, subject to
26 * the following conditions:
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
35 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
36 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
37 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40 #include <vlib/vlib.h>
41 #include <vlib/pci/pci.h>
42 #include <vlib/unix/unix.h>
44 #include <sys/types.h>
48 #include <sys/ioctl.h>
51 #include <linux/ethtool.h>
52 #include <linux/sockios.h>
53 #endif /* __linux__ */
55 vlib_pci_main_t pci_main;
57 VLIB_REGISTER_LOG_CLASS (pci_log, static) = {
61 #define log_debug(h, f, ...) \
62 vlib_log (VLIB_LOG_LEVEL_DEBUG, pci_log.class, "%U: " f, \
63 format_vlib_pci_log, h, ##__VA_ARGS__)
66 format_vlib_pci_log (u8 *s, va_list *va)
68 vlib_pci_dev_handle_t h = va_arg (*va, vlib_pci_dev_handle_t);
69 return format (s, "%U", format_vlib_pci_addr,
70 vlib_pci_get_addr (vlib_get_main (), h));
73 vlib_pci_device_info_t *__attribute__ ((weak))
74 vlib_pci_get_device_info (vlib_main_t *vm, vlib_pci_addr_t *addr,
78 *error = clib_error_return (0, "unsupported");
82 clib_error_t *__attribute__ ((weak))
83 vlib_pci_get_device_root_bus (vlib_pci_addr_t *addr, vlib_pci_addr_t *root_bus)
88 vlib_pci_addr_t * __attribute__ ((weak)) vlib_pci_get_all_dev_addrs ()
94 _vlib_pci_config_set_control_bit (vlib_main_t *vm, vlib_pci_dev_handle_t h,
95 u16 bit, int new_val, int *already_set)
100 err = vlib_pci_read_write_config (
101 vm, h, VLIB_READ, STRUCT_OFFSET_OF (vlib_pci_config_t, command), &old,
102 STRUCT_SIZE_OF (vlib_pci_config_t, command));
107 control = new_val ? old | bit : old & ~bit;
108 *already_set = old == control;
112 return vlib_pci_read_write_config (
113 vm, h, VLIB_WRITE, STRUCT_OFFSET_OF (vlib_pci_config_t, command), &control,
114 STRUCT_SIZE_OF (vlib_pci_config_t, command));
118 vlib_pci_intr_enable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
120 const vlib_pci_config_reg_command_t cmd = { .intx_disable = 1 };
124 err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 0, &already_set);
125 log_debug (h, "interrupt%senabled", already_set ? " " : " already ");
130 vlib_pci_intr_disable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
132 const vlib_pci_config_reg_command_t cmd = { .intx_disable = 1 };
136 err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 1, &already_set);
137 log_debug (h, "interrupt%sdisabled", already_set ? " " : " already ");
142 vlib_pci_bus_master_enable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
144 const vlib_pci_config_reg_command_t cmd = { .bus_master = 1 };
148 err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 1, &already_set);
149 log_debug (h, "bus-master%senabled", already_set ? " " : " already ");
154 vlib_pci_bus_master_disable (vlib_main_t *vm, vlib_pci_dev_handle_t h)
156 const vlib_pci_config_reg_command_t cmd = { .bus_master = 1 };
160 err = _vlib_pci_config_set_control_bit (vm, h, cmd.as_u16, 0, &already_set);
161 log_debug (h, "bus-master%sdisabled", already_set ? " " : " already ");
166 vlib_pci_function_level_reset (vlib_main_t *vm, vlib_pci_dev_handle_t h)
168 vlib_pci_config_t cfg;
169 pci_capability_pcie_t *cap;
170 pci_capability_pcie_dev_control_t dev_control;
174 log_debug (h, "function level reset");
176 err = vlib_pci_read_write_config (vm, h, VLIB_READ, 0, &cfg, sizeof (cfg));
180 offset = cfg.cap_ptr;
183 cap = (pci_capability_pcie_t *) (cfg.data + offset);
185 if (cap->capability_id == PCI_CAP_ID_PCIE)
188 offset = cap->next_offset;
192 if (cap->capability_id != PCI_CAP_ID_PCIE)
193 return clib_error_return (0, "PCIe capability config not found");
195 if (cap->dev_caps.flr_capable == 0)
196 return clib_error_return (0, "PCIe function level reset not supported");
198 dev_control = cap->dev_control;
199 dev_control.function_level_reset = 1;
201 if ((err = vlib_pci_write_config_u16 (
202 vm, h, offset + STRUCT_OFFSET_OF (pci_capability_pcie_t, dev_control),
203 &dev_control.as_u16)))
209 static clib_error_t *
210 show_pci_fn (vlib_main_t * vm,
211 unformat_input_t * input, vlib_cli_command_t * cmd)
213 vlib_pci_addr_t *addr = 0, *addrs;
217 while (unformat_check_input (input) != UNFORMAT_END_OF_INPUT)
219 if (unformat (input, "all"))
222 return clib_error_return (0, "unknown input `%U'",
223 format_unformat_error, input);
226 vlib_cli_output (vm, "%-13s%-5s%-12s%-14s%-16s%-32s%s",
227 "Address", "Sock", "VID:PID", "Link Speed", "Driver",
228 "Product Name", "Vital Product Data");
230 addrs = vlib_pci_get_all_dev_addrs ();
232 vec_foreach (addr, addrs)
234 vlib_pci_device_info_t *d;
235 d = vlib_pci_get_device_info (vm, addr, 0);
240 if (d->device_class != PCI_CLASS_NETWORK_ETHERNET && !show_all)
243 vec_reset_length (s);
244 if (d->numa_node >= 0)
245 s = format (s, " %d", d->numa_node);
248 vm, "%-13U%-5v%04x:%04x %-14U%-16s%-32v%U", format_vlib_pci_addr,
249 addr, s, d->vendor_id, d->device_id, format_vlib_pci_link_speed, d,
250 d->driver_name ? (char *) d->driver_name : "", d->product_name,
251 format_vlib_pci_vpd, d->vpd_r, (u8 *) 0);
252 vlib_pci_free_device_info (d);
261 unformat_vlib_pci_addr (unformat_input_t * input, va_list * args)
263 vlib_pci_addr_t *addr = va_arg (*args, vlib_pci_addr_t *);
266 if (!unformat (input, "%x:%x:%x.%x", &x[0], &x[1], &x[2], &x[3]))
272 addr->function = x[3];
278 format_vlib_pci_addr (u8 * s, va_list * va)
280 vlib_pci_addr_t *addr = va_arg (*va, vlib_pci_addr_t *);
281 return format (s, "%04x:%02x:%02x.%x", addr->domain, addr->bus,
282 addr->slot, addr->function);
286 format_vlib_pci_link_port (u8 *s, va_list *va)
288 vlib_pci_config_t *c = va_arg (*va, vlib_pci_config_t *);
289 pci_capability_pcie_t *r = pci_config_find_capability (c, PCI_CAP_ID_PCIE);
292 return format (s, "unknown");
294 return format (s, "P%d", r->link_caps.port_number);
298 _vlib_pci_link_speed (u8 *s, u8 speed, u8 width)
300 static char *speeds[] = {
301 [1] = "2.5", [2] = "5.0", [3] = "8.0", [4] = "16.0", [5] = "32.0"
304 if (speed >= ARRAY_LEN (speeds) || speeds[speed] == 0)
305 s = format (s, "unknown speed");
307 s = format (s, "%s GT/s", speeds[speed]);
309 return format (s, " x%u", width);
313 format_vlib_pci_link_speed (u8 *s, va_list *va)
315 vlib_pci_config_t *c = va_arg (*va, vlib_pci_config_t *);
316 pci_capability_pcie_t *r = pci_config_find_capability (c, PCI_CAP_ID_PCIE);
319 return format (s, "unknown");
321 return _vlib_pci_link_speed (s, r->link_status.link_speed,
322 r->link_status.negotiated_link_width);
326 format_vlib_pci_link_speed_cap (u8 *s, va_list *va)
328 vlib_pci_config_t *c = va_arg (*va, vlib_pci_config_t *);
329 pci_capability_pcie_t *r = pci_config_find_capability (c, PCI_CAP_ID_PCIE);
332 return format (s, "unknown");
334 return _vlib_pci_link_speed (s, r->link_caps.max_link_speed,
335 r->link_caps.max_link_width);
339 format_vlib_pci_vpd (u8 * s, va_list * args)
341 u8 *data = va_arg (*args, u8 *);
342 u8 *id = va_arg (*args, u8 *);
343 u32 indent = format_get_indent (s);
344 char *string_types[] = { "PN", "EC", "SN", "MN", 0 };
348 if (vec_len (data) < 3)
351 while (p + 3 < vec_len (data))
354 if (data[p] == 0 && data[p + 1] == 0)
357 if (p + data[p + 2] > vec_len (data))
363 char **c = string_types;
367 if (*(u16 *) & data[p] == *(u16 *) c[0])
375 s = format (s, "\n%U", format_white_space, indent);
382 s = format (s, "%c%c: ", data[p], data[p + 1]);
384 vec_add (s, data + p + 3, data[p + 2]);
388 const int max_bytes = 8;
389 s = format (s, "0x");
390 for (i = 0; i < clib_min (data[p + 2], max_bytes); i++)
391 s = format (s, " %02x", data[p + 3 + i]);
393 if (data[p + 2] > max_bytes)
394 s = format (s, " ...");
398 else if (*(u16 *) & data[p] == *(u16 *) id)
400 vec_add (s, data + p + 3, data[p + 2]);
404 p += 3 + data[p + 2];
410 VLIB_CLI_COMMAND (show_pci_command, static) = {
412 .short_help = "show pci [all]",
413 .function = show_pci_fn,