2 * Copyright (c) 2016 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 * pci.h: PCI definitions.
18 * Copyright (c) 2008 Eliot Dresselhaus
20 * Permission is hereby granted, free of charge, to any person obtaining
21 * a copy of this software and associated documentation files (the
22 * "Software"), to deal in the Software without restriction, including
23 * without limitation the rights to use, copy, modify, merge, publish,
24 * distribute, sublicense, and/or sell copies of the Software, and to
25 * permit persons to whom the Software is furnished to do so, subject to
26 * the following conditions:
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
35 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
36 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
37 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40 #ifndef included_vlib_pci_config_h
41 #define included_vlib_pci_config_h
43 #include <vppinfra/byte_order.h>
44 #include <vppinfra/error.h>
48 PCI_CLASS_NOT_DEFINED = 0x0000,
49 PCI_CLASS_NOT_DEFINED_VGA = 0x0001,
51 PCI_CLASS_STORAGE_SCSI = 0x0100,
52 PCI_CLASS_STORAGE_IDE = 0x0101,
53 PCI_CLASS_STORAGE_FLOPPY = 0x0102,
54 PCI_CLASS_STORAGE_IPI = 0x0103,
55 PCI_CLASS_STORAGE_RAID = 0x0104,
56 PCI_CLASS_STORAGE_OTHER = 0x0180,
57 PCI_CLASS_STORAGE = 0x0100,
59 PCI_CLASS_NETWORK_ETHERNET = 0x0200,
60 PCI_CLASS_NETWORK_TOKEN_RING = 0x0201,
61 PCI_CLASS_NETWORK_FDDI = 0x0202,
62 PCI_CLASS_NETWORK_ATM = 0x0203,
63 PCI_CLASS_NETWORK_OTHER = 0x0280,
64 PCI_CLASS_NETWORK = 0x0200,
66 PCI_CLASS_DISPLAY_VGA = 0x0300,
67 PCI_CLASS_DISPLAY_XGA = 0x0301,
68 PCI_CLASS_DISPLAY_3D = 0x0302,
69 PCI_CLASS_DISPLAY_OTHER = 0x0380,
70 PCI_CLASS_DISPLAY = 0x0300,
72 PCI_CLASS_MULTIMEDIA_VIDEO = 0x0400,
73 PCI_CLASS_MULTIMEDIA_AUDIO = 0x0401,
74 PCI_CLASS_MULTIMEDIA_PHONE = 0x0402,
75 PCI_CLASS_MULTIMEDIA_OTHER = 0x0480,
76 PCI_CLASS_MULTIMEDIA = 0x0400,
78 PCI_CLASS_MEMORY_RAM = 0x0500,
79 PCI_CLASS_MEMORY_FLASH = 0x0501,
80 PCI_CLASS_MEMORY_OTHER = 0x0580,
81 PCI_CLASS_MEMORY = 0x0500,
83 PCI_CLASS_BRIDGE_HOST = 0x0600,
84 PCI_CLASS_BRIDGE_ISA = 0x0601,
85 PCI_CLASS_BRIDGE_EISA = 0x0602,
86 PCI_CLASS_BRIDGE_MC = 0x0603,
87 PCI_CLASS_BRIDGE_PCI = 0x0604,
88 PCI_CLASS_BRIDGE_PCMCIA = 0x0605,
89 PCI_CLASS_BRIDGE_NUBUS = 0x0606,
90 PCI_CLASS_BRIDGE_CARDBUS = 0x0607,
91 PCI_CLASS_BRIDGE_RACEWAY = 0x0608,
92 PCI_CLASS_BRIDGE_OTHER = 0x0680,
93 PCI_CLASS_BRIDGE = 0x0600,
95 PCI_CLASS_COMMUNICATION_SERIAL = 0x0700,
96 PCI_CLASS_COMMUNICATION_PARALLEL = 0x0701,
97 PCI_CLASS_COMMUNICATION_MULTISERIAL = 0x0702,
98 PCI_CLASS_COMMUNICATION_MODEM = 0x0703,
99 PCI_CLASS_COMMUNICATION_OTHER = 0x0780,
100 PCI_CLASS_COMMUNICATION = 0x0700,
102 PCI_CLASS_SYSTEM_PIC = 0x0800,
103 PCI_CLASS_SYSTEM_DMA = 0x0801,
104 PCI_CLASS_SYSTEM_TIMER = 0x0802,
105 PCI_CLASS_SYSTEM_RTC = 0x0803,
106 PCI_CLASS_SYSTEM_PCI_HOTPLUG = 0x0804,
107 PCI_CLASS_SYSTEM_OTHER = 0x0880,
108 PCI_CLASS_SYSTEM = 0x0800,
110 PCI_CLASS_INPUT_KEYBOARD = 0x0900,
111 PCI_CLASS_INPUT_PEN = 0x0901,
112 PCI_CLASS_INPUT_MOUSE = 0x0902,
113 PCI_CLASS_INPUT_SCANNER = 0x0903,
114 PCI_CLASS_INPUT_GAMEPORT = 0x0904,
115 PCI_CLASS_INPUT_OTHER = 0x0980,
116 PCI_CLASS_INPUT = 0x0900,
118 PCI_CLASS_DOCKING_GENERIC = 0x0a00,
119 PCI_CLASS_DOCKING_OTHER = 0x0a80,
120 PCI_CLASS_DOCKING = 0x0a00,
122 PCI_CLASS_PROCESSOR_386 = 0x0b00,
123 PCI_CLASS_PROCESSOR_486 = 0x0b01,
124 PCI_CLASS_PROCESSOR_PENTIUM = 0x0b02,
125 PCI_CLASS_PROCESSOR_ALPHA = 0x0b10,
126 PCI_CLASS_PROCESSOR_POWERPC = 0x0b20,
127 PCI_CLASS_PROCESSOR_MIPS = 0x0b30,
128 PCI_CLASS_PROCESSOR_CO = 0x0b40,
129 PCI_CLASS_PROCESSOR = 0x0b00,
131 PCI_CLASS_SERIAL_FIREWIRE = 0x0c00,
132 PCI_CLASS_SERIAL_ACCESS = 0x0c01,
133 PCI_CLASS_SERIAL_SSA = 0x0c02,
134 PCI_CLASS_SERIAL_USB = 0x0c03,
135 PCI_CLASS_SERIAL_FIBER = 0x0c04,
136 PCI_CLASS_SERIAL_SMBUS = 0x0c05,
137 PCI_CLASS_SERIAL = 0x0c00,
139 PCI_CLASS_INTELLIGENT_I2O = 0x0e00,
140 PCI_CLASS_INTELLIGENT = 0x0e00,
142 PCI_CLASS_SATELLITE_TV = 0x0f00,
143 PCI_CLASS_SATELLITE_AUDIO = 0x0f01,
144 PCI_CLASS_SATELLITE_VOICE = 0x0f03,
145 PCI_CLASS_SATELLITE_DATA = 0x0f04,
146 PCI_CLASS_SATELLITE = 0x0f00,
148 PCI_CLASS_CRYPT_NETWORK = 0x1000,
149 PCI_CLASS_CRYPT_ENTERTAINMENT = 0x1001,
150 PCI_CLASS_CRYPT_OTHER = 0x1080,
151 PCI_CLASS_CRYPT = 0x1000,
153 PCI_CLASS_SP_DPIO = 0x1100,
154 PCI_CLASS_SP_OTHER = 0x1180,
155 PCI_CLASS_SP = 0x1100,
156 } pci_device_class_t;
158 static inline pci_device_class_t
159 pci_device_class_base (pci_device_class_t c)
165 * 0x1000 is the legacy device-id value
166 * 0x1041 is (0x1040 + 1), 1 being the Virtio Device ID
168 #define VIRTIO_PCI_LEGACY_DEVICEID_NET 0x1000
169 #define VIRTIO_PCI_MODERN_DEVICEID_NET 0x1041
178 u16 special_cycles : 1;
179 u16 mem_write_invalidate : 1;
180 u16 vga_palette_snoop : 1;
181 u16 parity_err_resp : 1;
184 u16 fast_b2b_enable : 1;
185 u16 intx_disable : 1;
186 u16 _reserved_11 : 5;
189 } vlib_pci_config_reg_command_t;
197 u16 capabilities_list : 1;
198 u16 capaable_66mhz : 1;
200 u16 fast_b2b_capable : 1;
201 u16 master_data_parity_error : 1;
202 u16 devsel_timing : 2;
203 u16 sig_target_abort : 1;
204 u16 rec_target_abort : 1;
205 u16 rec_master_abort : 1;
206 u16 sig_system_err : 1;
207 u16 detected_parity_err : 1;
210 } vlib_pci_config_reg_status_t;
214 PCI_HEADER_TYPE_NORMAL = 0,
215 PCI_HEADER_TYPE_BRIDGE = 1,
216 PCI_HEADER_TYPE_CARDBUS = 2
217 } __clib_packed pci_config_header_type_t;
219 #define foreach_pci_config_reg \
222 _ (vlib_pci_config_reg_command_t, command) \
223 _ (vlib_pci_config_reg_status_t, status) \
224 _ (u8, revision_id) \
228 _ (u8, cache_line_size) \
229 _ (u8, latency_timer) \
230 _ (pci_config_header_type_t, header_type) \
233 _ (u32, cardbus_cis_ptr) \
234 _ (u16, sub_vendor_id) \
235 _ (u16, sub_device_id) \
236 _ (u32, exp_rom_base_addr) \
238 _ (u8, _reserved_0x35, [3]) \
239 _ (u32, _reserved_0x38) \
247 #define _(a, b, ...) a b __VA_ARGS__;
248 foreach_pci_config_reg
250 } vlib_pci_config_hdr_t;
252 STATIC_ASSERT_SIZEOF (vlib_pci_config_hdr_t, 64);
258 #define _(a, b, ...) a b __VA_ARGS__;
259 foreach_pci_config_reg
265 STATIC_ASSERT_SIZEOF (vlib_pci_config_t, 256);
271 #define _(a, b, ...) a b __VA_ARGS__;
272 foreach_pci_config_reg
276 } vlib_pci_config_ext_t;
278 STATIC_ASSERT_SIZEOF (vlib_pci_config_ext_t, 4096);
281 typedef enum pci_capability_type
283 /* Power Management */
286 /* Accelerated Graphics Port */
289 /* Vital Product Data */
292 /* Slot Identification */
293 PCI_CAP_ID_SLOTID = 4,
295 /* Message Signalled Interrupts */
298 /* CompactPCI HotSwap */
299 PCI_CAP_ID_CHSWP = 6,
304 /* Hypertransport. */
305 PCI_CAP_ID_HYPERTRANSPORT = 8,
307 /* PCI Standard Hot-Plug Controller */
308 PCI_CAP_ID_SHPC = 0xc,
311 PCI_CAP_ID_PCIE = 0x10,
314 PCI_CAP_ID_MSIX = 0x11,
315 } pci_capability_type_t;
317 /* Common header for capabilities. */
320 enum pci_capability_type type:8;
322 } __clib_packed pci_capability_regs_t;
325 pci_config_find_capability (vlib_pci_config_t *t, int cap_type)
327 pci_capability_regs_t *c;
331 if (!(t->status.capabilities_list))
334 next_offset = t->cap_ptr;
335 while (ttl-- && next_offset >= 0x40)
337 c = (void *) t + (next_offset & ~3);
338 if ((u8) c->type == 0xff)
340 if (c->type == cap_type)
342 next_offset = c->next_offset;
347 /* Power Management Registers */
350 pci_capability_regs_t header;
352 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
353 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
354 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
355 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
356 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
357 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
358 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
359 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
360 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
361 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
362 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
363 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
364 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
365 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
367 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
368 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
369 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
370 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
371 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
373 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
374 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
376 } __clib_packed pci_power_management_regs_t;
381 pci_capability_regs_t header;
383 u8 rest_of_capability_flags;
386 /* Command & status common bits. */
387 #define PCI_AGP_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
388 #define PCI_AGP_SBA 0x0200 /* Sideband addressing supported */
389 #define PCI_AGP_64BIT 0x0020 /* 64-bit addressing supported */
390 #define PCI_AGP_ALLOW_TRANSACTIONS 0x0100 /* Allow processing of AGP transactions */
391 #define PCI_AGP_FW 0x0010 /* FW transfers supported/forced */
392 #define PCI_AGP_RATE4 0x0004 /* 4x transfer rate supported */
393 #define PCI_AGP_RATE2 0x0002 /* 2x transfer rate supported */
394 #define PCI_AGP_RATE1 0x0001 /* 1x transfer rate supported */
395 } __clib_packed pci_agp_regs_t;
397 /* Vital Product Data */
400 pci_capability_regs_t header;
402 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
403 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
405 } __clib_packed pci_vpd_regs_t;
407 /* Slot Identification */
410 pci_capability_regs_t header;
412 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
413 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
415 } __clib_packed pci_sid_regs_t;
417 /* Message Signalled Interrupts registers */
420 pci_capability_regs_t header;
422 #define PCI_MSI_FLAGS_ENABLE (1 << 0) /* MSI feature enabled */
423 #define PCI_MSI_FLAGS_GET_MAX_QUEUE_SIZE(x) ((x >> 1) & 0x7)
424 #define PCI_MSI_FLAGS_MAX_QUEUE_SIZE(x) (((x) & 0x7) << 1)
425 #define PCI_MSI_FLAGS_GET_QUEUE_SIZE(x) ((x >> 4) & 0x7)
426 #define PCI_MSI_FLAGS_QUEUE_SIZE(x) (((x) & 0x7) << 4)
427 #define PCI_MSI_FLAGS_64BIT (1 << 7) /* 64-bit addresses allowed */
428 #define PCI_MSI_FLAGS_MASKBIT (1 << 8) /* 64-bit mask bits allowed */
432 } __clib_packed pci_msi32_regs_t;
436 pci_capability_regs_t header;
441 } __clib_packed pci_msi64_regs_t;
443 /* CompactPCI Hotswap Register */
446 pci_capability_regs_t header;
448 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
449 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
450 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
451 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */
452 #define PCI_CHSWP_PI 0x30 /* Programming Interface */
453 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
454 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
455 } __clib_packed pci_chswp_regs_t;
460 pci_capability_regs_t header;
462 #define PCIX_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
463 #define PCIX_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
464 #define PCIX_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
465 #define PCIX_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
466 #define PCIX_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
468 #define PCIX_STATUS_DEVFN 0x000000ff /* A copy of devfn */
469 #define PCIX_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
470 #define PCIX_STATUS_64BIT 0x00010000 /* 64-bit device */
471 #define PCIX_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
472 #define PCIX_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
473 #define PCIX_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
474 #define PCIX_STATUS_COMPLEX 0x00100000 /* Device Complexity */
475 #define PCIX_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
476 #define PCIX_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
477 #define PCIX_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
478 #define PCIX_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
479 #define PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
480 #define PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
481 } __clib_packed pcix_config_regs_t;
484 pcie_size_to_code (int bytes)
486 ASSERT (is_pow2 (bytes));
487 ASSERT (bytes <= 4096);
488 return min_log2 (bytes) - 7;
492 pcie_code_to_size (int code)
494 int size = 1 << (code + 7);
495 ASSERT (size <= 4096);
499 /* PCI express extended capabilities. */
500 typedef enum pcie_capability_type
502 PCIE_CAP_ADVANCED_ERROR = 1,
506 } pcie_capability_type_t;
508 /* Common header for capabilities. */
511 enum pcie_capability_type type:16;
513 u16 next_capability:12;
514 } __clib_packed pcie_capability_regs_t;
518 pcie_capability_regs_t header;
519 u32 uncorrectable_status;
520 #define PCIE_ERROR_UNC_LINK_TRAINING (1 << 0)
521 #define PCIE_ERROR_UNC_DATA_LINK_PROTOCOL (1 << 4)
522 #define PCIE_ERROR_UNC_SURPRISE_DOWN (1 << 5)
523 #define PCIE_ERROR_UNC_POISONED_TLP (1 << 12)
524 #define PCIE_ERROR_UNC_FLOW_CONTROL (1 << 13)
525 #define PCIE_ERROR_UNC_COMPLETION_TIMEOUT (1 << 14)
526 #define PCIE_ERROR_UNC_COMPLETER_ABORT (1 << 15)
527 #define PCIE_ERROR_UNC_UNEXPECTED_COMPLETION (1 << 16)
528 #define PCIE_ERROR_UNC_RX_OVERFLOW (1 << 17)
529 #define PCIE_ERROR_UNC_MALFORMED_TLP (1 << 18)
530 #define PCIE_ERROR_UNC_CRC_ERROR (1 << 19)
531 #define PCIE_ERROR_UNC_UNSUPPORTED_REQUEST (1 << 20)
532 u32 uncorrectable_mask;
533 u32 uncorrectable_severity;
534 u32 correctable_status;
535 #define PCIE_ERROR_COR_RX_ERROR (1 << 0)
536 #define PCIE_ERROR_COR_BAD_TLP (1 << 6)
537 #define PCIE_ERROR_COR_BAD_DLLP (1 << 7)
538 #define PCIE_ERROR_COR_REPLAY_ROLLOVER (1 << 8)
539 #define PCIE_ERROR_COR_REPLAY_TIMER (1 << 12)
540 #define PCIE_ERROR_COR_ADVISORY (1 << 13)
541 u32 correctable_mask;
546 u16 correctable_error_source;
548 } __clib_packed pcie_advanced_error_regs_t;
550 /* Virtual Channel */
551 #define PCI_VC_PORT_REG1 4
552 #define PCI_VC_PORT_REG2 8
553 #define PCI_VC_PORT_CTRL 12
554 #define PCI_VC_PORT_STATUS 14
555 #define PCI_VC_RES_CAP 16
556 #define PCI_VC_RES_CTRL 20
557 #define PCI_VC_RES_STATUS 26
559 /* Power Budgeting */
560 #define PCI_PWR_DSR 4 /* Data Select Register */
561 #define PCI_PWR_DATA 8 /* Data Register */
562 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
563 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
564 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
565 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
566 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
567 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
568 #define PCI_PWR_CAP 12 /* Capability */
569 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
571 #define pci_capability_pcie_dev_caps_t_fields \
572 _ (3, max_payload_sz) \
573 _ (2, phantom_fn_present) \
574 _ (1, ext_tags_supported) \
575 _ (3, acceptable_l0s_latency) \
576 _ (3, acceptable_l1_latency) \
577 _ (1, attention_button_present) \
578 _ (1, attention_indicator_present) \
579 _ (1, power_indicator_present) \
580 _ (1, role_based_error_reporting_supported) \
581 _ (2, _reserved_16) \
582 _ (8, slot_ppower_limit_val) \
583 _ (2, slot_power_limit_scale) \
587 #define pci_capability_pcie_dev_control_t_fields \
588 _ (1, enable_correctable_error_reporting) \
589 _ (1, enable_non_fatal_error_reporting) \
590 _ (1, enable_fatal_error_reporting) \
591 _ (1, enable_unsupported_request_reporting) \
592 _ (1, enable_relaxed_ordering) \
593 _ (3, maximum_payload_size) \
594 _ (1, extended_tag_field_enable) \
595 _ (1, phantom_fn_denable) \
596 _ (1, aux_power_pm_enable) \
597 _ (1, enable_no_snoop) \
598 _ (3, max_read_request_size) \
599 _ (1, function_level_reset)
601 #define pci_capability_pcie_dev_status_t_fields \
602 _ (1, correctable_err_detected) \
603 _ (1, non_fatal_err_detected) \
604 _ (1, fatal_err_detected) \
605 _ (1, unsupported_request_detected) \
606 _ (1, aux_power_detected) \
607 _ (1, transaction_pending) \
610 #define pci_capability_pcie_link_caps_t_fields \
611 _ (4, max_link_speed) \
612 _ (5, max_link_width) \
613 _ (2, aspm_support) \
614 _ (3, l0s_exit_latency) \
615 _ (3, l1_exit_latency) \
616 _ (1, clock_power_mgmt_status) \
617 _ (1, surprise_down_error_reporting_capable_status) \
618 _ (1, data_link_layer_link_active_reporting_capable_status) \
619 _ (1, link_bandwidth_notification_capability_status) \
620 _ (1, aspm_optionality_compliance) \
621 _ (1, _reserved_23) \
624 #define pci_capability_pcie_link_control_t_fields \
625 _ (2, aspm_control) \
627 _ (1, read_completion_boundary) \
628 _ (1, link_disable) \
629 _ (1, retrain_clock) \
630 _ (1, common_clock_config) \
631 _ (1, extended_synch) \
632 _ (1, enable_clock_pwr_mgmt) \
633 _ (1, hw_autonomous_width_disable) \
634 _ (1, link_bw_mgmt_intr_enable) \
635 _ (1, link_autonomous_bw_intr_enable) \
638 #define pci_capability_pcie_link_status_t_fields \
640 _ (6, negotiated_link_width) \
641 _ (1, _reserved_10) \
642 _ (1, link_training) \
643 _ (1, slot_clock_config) \
644 _ (1, data_link_layer_link_active) \
645 _ (1, link_bw_mgmt_status) \
648 #define pci_capability_pcie_dev_caps2_t_fields \
649 _ (4, compl_timeout_ranges_supported) \
650 _ (1, compl_timeout_disable_supported) \
651 _ (1, ari_forwarding_supported) \
652 _ (1, atomic_op_routing_supported) \
653 _ (1, bit32_atomic_op_completer_supported) \
654 _ (1, bit64_atomic_op_completer_supported) \
655 _ (1, bit128_cas_completer_supported) \
656 _ (1, no_ro_enabled_pr_pr_passing) \
657 _ (1, ltr_mechanism_supported) \
658 _ (1, tph_completer_supported) \
661 #define pci_capability_pcie_dev_control2_t_fields \
662 _ (4, completion_timeout_value) \
663 _ (1, completion_timeout_disable) \
664 _ (1, ari_forwarding_enable) \
665 _ (1, atomic_op_requester_enable) \
666 _ (1, atomic_op_egress_blocking) \
667 _ (1, ido_request_enable) \
668 _ (1, ido_completion_enable) \
669 _ (1, ltr_mechanism_enable) \
672 #define pci_capability_pcie_link_control2_t_fields \
673 _ (4, target_link_speed) \
674 _ (1, enter_compliance) \
675 _ (1, hw_autonomous_speed_disable) \
676 _ (1, selectable_de_emphasis) \
677 _ (3, transmit_margin) \
678 _ (1, enter_modified_compliance) \
679 _ (1, compliance_sos) \
680 _ (4, compliance_de_emphasis)
682 #define pci_capability_pcie_link_status2_t_fields \
683 _ (1, current_de_emphasis_level) \
695 STATIC_ASSERT_SIZEOF (n, sizeof (t))
697 #define _(b, n) u32 n : b;
698 __ (u32, pci_capability_pcie_dev_caps_t);
699 __ (u32, pci_capability_pcie_link_caps_t);
700 __ (u32, pci_capability_pcie_dev_caps2_t);
702 #define _(b, n) u16 n : b;
703 __ (u16, pci_capability_pcie_dev_control_t);
704 __ (u16, pci_capability_pcie_dev_status_t);
705 __ (u16, pci_capability_pcie_link_control_t);
706 __ (u16, pci_capability_pcie_link_status_t);
707 __ (u16, pci_capability_pcie_dev_control2_t);
708 __ (u16, pci_capability_pcie_link_control2_t);
709 __ (u16, pci_capability_pcie_link_status2_t);
718 u16 _reserved_0_19 : 13;
719 pci_capability_pcie_dev_caps_t dev_caps;
720 pci_capability_pcie_dev_control_t dev_control;
721 pci_capability_pcie_dev_status_t dev_status;
722 pci_capability_pcie_link_caps_t link_caps;
723 pci_capability_pcie_link_control_t link_control;
724 pci_capability_pcie_link_status_t link_status;
731 pci_capability_pcie_dev_caps2_t dev_caps2;
732 pci_capability_pcie_dev_control2_t dev_control2;
735 pci_capability_pcie_link_control2_t link_control2;
736 pci_capability_pcie_link_status2_t link_status2;
740 } pci_capability_pcie_t;
742 STATIC_ASSERT_SIZEOF (pci_capability_pcie_t, 60);
744 #endif /* included_vlib_pci_config_h */