2 * Copyright (c) 2016 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
18 * This driver is not intended for production use and it is unsupported.
19 * It is provided for educational use only.
20 * Please use supported DPDK driver instead.
24 #include <vppinfra/vector.h>
26 #ifndef CLIB_HAVE_VEC128
27 #warning HACK: ixge driver wont really work, missing u32x4
28 typedef unsigned long long u32x4;
31 #include <vlib/vlib.h>
32 #include <vlib/unix/unix.h>
33 #include <vlib/pci/pci.h>
34 #include <vnet/vnet.h>
35 #include <vnet/devices/nic/ixge.h>
36 #include <vnet/ethernet/ethernet.h>
38 #define IXGE_ALWAYS_POLL 0
40 #define EVENT_SET_FLAGS 0
41 #define IXGE_HWBP_RACE_ELOG 0
43 #define PCI_VENDOR_ID_INTEL 0x8086
45 /* 10 GIG E (XGE) PHY IEEE 802.3 clause 45 definitions. */
46 #define XGE_PHY_DEV_TYPE_PMA_PMD 1
47 #define XGE_PHY_DEV_TYPE_PHY_XS 4
48 #define XGE_PHY_ID1 0x2
49 #define XGE_PHY_ID2 0x3
50 #define XGE_PHY_CONTROL 0x0
51 #define XGE_PHY_CONTROL_RESET (1 << 15)
53 ixge_main_t ixge_main;
54 static vlib_node_registration_t ixge_input_node;
55 static vlib_node_registration_t ixge_process_node;
58 ixge_semaphore_get (ixge_device_t * xd)
60 ixge_main_t *xm = &ixge_main;
61 vlib_main_t *vm = xm->vlib_main;
62 ixge_regs_t *r = xd->regs;
66 while (!(r->software_semaphore & (1 << 0)))
69 vlib_process_suspend (vm, 100e-6);
74 r->software_semaphore |= 1 << 1;
76 while (!(r->software_semaphore & (1 << 1)));
80 ixge_semaphore_release (ixge_device_t * xd)
82 ixge_regs_t *r = xd->regs;
83 r->software_semaphore &= ~3;
87 ixge_software_firmware_sync (ixge_device_t * xd, u32 sw_mask)
89 ixge_main_t *xm = &ixge_main;
90 vlib_main_t *vm = xm->vlib_main;
91 ixge_regs_t *r = xd->regs;
92 u32 fw_mask = sw_mask << 5;
97 ixge_semaphore_get (xd);
98 m = r->software_firmware_sync;
99 done = (m & fw_mask) == 0;
101 r->software_firmware_sync = m | sw_mask;
102 ixge_semaphore_release (xd);
104 vlib_process_suspend (vm, 10e-3);
109 ixge_software_firmware_sync_release (ixge_device_t * xd, u32 sw_mask)
111 ixge_regs_t *r = xd->regs;
112 ixge_semaphore_get (xd);
113 r->software_firmware_sync &= ~sw_mask;
114 ixge_semaphore_release (xd);
118 ixge_read_write_phy_reg (ixge_device_t * xd, u32 dev_type, u32 reg_index,
121 ixge_regs_t *r = xd->regs;
122 const u32 busy_bit = 1 << 30;
125 ASSERT (xd->phy_index < 2);
126 ixge_software_firmware_sync (xd, 1 << (1 + xd->phy_index));
128 ASSERT (reg_index < (1 << 16));
129 ASSERT (dev_type < (1 << 5));
131 r->xge_mac.phy_data = v;
135 reg_index | (dev_type << 16) | (xd->
136 phys[xd->phy_index].mdio_address << 21);
137 r->xge_mac.phy_command = x | busy_bit;
138 /* Busy wait timed to take 28e-6 secs. No suspend. */
139 while (r->xge_mac.phy_command & busy_bit)
142 r->xge_mac.phy_command = x | ((is_read ? 2 : 1) << 26) | busy_bit;
143 while (r->xge_mac.phy_command & busy_bit)
147 v = r->xge_mac.phy_data >> 16;
149 ixge_software_firmware_sync_release (xd, 1 << (1 + xd->phy_index));
155 ixge_read_phy_reg (ixge_device_t * xd, u32 dev_type, u32 reg_index)
157 return ixge_read_write_phy_reg (xd, dev_type, reg_index, 0, /* is_read */
162 ixge_write_phy_reg (ixge_device_t * xd, u32 dev_type, u32 reg_index, u32 v)
164 (void) ixge_read_write_phy_reg (xd, dev_type, reg_index, v, /* is_read */
169 ixge_i2c_put_bits (i2c_bus_t * b, int scl, int sda)
171 ixge_main_t *xm = &ixge_main;
172 ixge_device_t *xd = vec_elt_at_index (xm->devices, b->private_data);
176 v |= (sda != 0) << 3;
177 v |= (scl != 0) << 1;
178 xd->regs->i2c_control = v;
182 ixge_i2c_get_bits (i2c_bus_t * b, int *scl, int *sda)
184 ixge_main_t *xm = &ixge_main;
185 ixge_device_t *xd = vec_elt_at_index (xm->devices, b->private_data);
188 v = xd->regs->i2c_control;
189 *sda = (v & (1 << 2)) != 0;
190 *scl = (v & (1 << 0)) != 0;
194 ixge_read_eeprom (ixge_device_t * xd, u32 address)
196 ixge_regs_t *r = xd->regs;
198 r->eeprom_read = (( /* start bit */ (1 << 0)) | (address << 2));
199 /* Wait for done bit. */
200 while (!((v = r->eeprom_read) & (1 << 1)))
206 ixge_sfp_enable_disable_laser (ixge_device_t * xd, uword enable)
208 u32 tx_disable_bit = 1 << 3;
210 xd->regs->sdp_control &= ~tx_disable_bit;
212 xd->regs->sdp_control |= tx_disable_bit;
216 ixge_sfp_enable_disable_10g (ixge_device_t * xd, uword enable)
218 u32 is_10g_bit = 1 << 5;
220 xd->regs->sdp_control |= is_10g_bit;
222 xd->regs->sdp_control &= ~is_10g_bit;
225 static clib_error_t *
226 ixge_sfp_phy_init_from_eeprom (ixge_device_t * xd, u16 sfp_type)
228 u16 a, id, reg_values_addr = 0;
230 a = ixge_read_eeprom (xd, 0x2b);
231 if (a == 0 || a == 0xffff)
232 return clib_error_create ("no init sequence in eeprom");
236 id = ixge_read_eeprom (xd, ++a);
239 reg_values_addr = ixge_read_eeprom (xd, ++a);
244 return clib_error_create ("failed to find id 0x%x", sfp_type);
246 ixge_software_firmware_sync (xd, 1 << 3);
249 u16 v = ixge_read_eeprom (xd, ++reg_values_addr);
252 xd->regs->core_analog_config = v;
254 ixge_software_firmware_sync_release (xd, 1 << 3);
256 /* Make sure laser is off. We'll turn on the laser when
257 the interface is brought up. */
258 ixge_sfp_enable_disable_laser (xd, /* enable */ 0);
259 ixge_sfp_enable_disable_10g (xd, /* is_10g */ 1);
265 ixge_sfp_device_up_down (ixge_device_t * xd, uword is_up)
271 /* pma/pmd 10g serial SFI. */
272 xd->regs->xge_mac.auto_negotiation_control2 &= ~(3 << 16);
273 xd->regs->xge_mac.auto_negotiation_control2 |= 2 << 16;
275 v = xd->regs->xge_mac.auto_negotiation_control;
278 /* Restart autoneg. */
280 xd->regs->xge_mac.auto_negotiation_control = v;
282 while (!(xd->regs->xge_mac.link_partner_ability[0] & 0xf0000))
285 v = xd->regs->xge_mac.auto_negotiation_control;
287 /* link mode 10g sfi serdes */
291 /* Restart autoneg. */
293 xd->regs->xge_mac.auto_negotiation_control = v;
295 xd->regs->xge_mac.link_status;
298 ixge_sfp_enable_disable_laser (xd, /* enable */ is_up);
300 /* Give time for link partner to notice that we're up. */
301 if (is_up && vlib_in_process_context (vlib_get_main ()))
303 vlib_process_suspend (vlib_get_main (), 300e-3);
307 always_inline ixge_dma_regs_t *
308 get_dma_regs (ixge_device_t * xd, vlib_rx_or_tx_t rt, u32 qi)
310 ixge_regs_t *r = xd->regs;
313 return qi < 64 ? &r->rx_dma0[qi] : &r->rx_dma1[qi - 64];
315 return &r->tx_dma[qi];
318 static clib_error_t *
319 ixge_interface_admin_up_down (vnet_main_t * vnm, u32 hw_if_index, u32 flags)
321 vnet_hw_interface_t *hif = vnet_get_hw_interface (vnm, hw_if_index);
322 uword is_up = (flags & VNET_SW_INTERFACE_FLAG_ADMIN_UP) != 0;
323 ixge_main_t *xm = &ixge_main;
324 ixge_device_t *xd = vec_elt_at_index (xm->devices, hif->dev_instance);
325 ixge_dma_regs_t *dr = get_dma_regs (xd, VLIB_RX, 0);
329 xd->regs->rx_enable |= 1;
330 xd->regs->tx_dma_control |= 1;
331 dr->control |= 1 << 25;
332 while (!(dr->control & (1 << 25)))
337 xd->regs->rx_enable &= ~1;
338 xd->regs->tx_dma_control &= ~1;
341 ixge_sfp_device_up_down (xd, is_up);
343 return /* no error */ 0;
347 ixge_sfp_phy_init (ixge_device_t * xd)
349 ixge_phy_t *phy = xd->phys + xd->phy_index;
350 i2c_bus_t *ib = &xd->i2c_bus;
352 ib->private_data = xd->device_index;
353 ib->put_bits = ixge_i2c_put_bits;
354 ib->get_bits = ixge_i2c_get_bits;
357 vlib_i2c_read_eeprom (ib, 0x50, 0, 128, (u8 *) & xd->sfp_eeprom);
359 if (vlib_i2c_bus_timed_out (ib) || !sfp_eeprom_is_valid (&xd->sfp_eeprom))
360 xd->sfp_eeprom.id = SFP_ID_unknown;
363 /* FIXME 5 => SR/LR eeprom ID. */
365 ixge_sfp_phy_init_from_eeprom (xd, 5 + xd->pci_function);
367 clib_error_report (e);
370 phy->mdio_address = ~0;
374 ixge_phy_init (ixge_device_t * xd)
376 ixge_main_t *xm = &ixge_main;
377 vlib_main_t *vm = xm->vlib_main;
378 ixge_phy_t *phy = xd->phys + xd->phy_index;
380 switch (xd->device_id)
383 case IXGE_82599_sfp_em:
384 case IXGE_82599_sfp_fcoe:
386 return ixge_sfp_phy_init (xd);
392 /* Probe address of phy. */
396 phy->mdio_address = ~0;
397 for (i = 0; i < 32; i++)
399 phy->mdio_address = i;
400 v = ixge_read_phy_reg (xd, XGE_PHY_DEV_TYPE_PMA_PMD, XGE_PHY_ID1);
401 if (v != 0xffff && v != 0)
411 ((ixge_read_phy_reg (xd, XGE_PHY_DEV_TYPE_PMA_PMD, XGE_PHY_ID1) << 16) |
412 ixge_read_phy_reg (xd, XGE_PHY_DEV_TYPE_PMA_PMD, XGE_PHY_ID2));
415 ELOG_TYPE_DECLARE (e) =
417 .function = (char *) __FUNCTION__,.format =
418 "ixge %d, phy id 0x%d mdio address %d",.format_args = "i4i4i4",};
421 u32 instance, id, address;
423 ed = ELOG_DATA (&vm->elog_main, e);
424 ed->instance = xd->device_index;
426 ed->address = phy->mdio_address;
430 ixge_write_phy_reg (xd, XGE_PHY_DEV_TYPE_PHY_XS, XGE_PHY_CONTROL,
431 XGE_PHY_CONTROL_RESET);
433 /* Wait for self-clearning reset bit to clear. */
436 vlib_process_suspend (vm, 1e-3);
438 while (ixge_read_phy_reg (xd, XGE_PHY_DEV_TYPE_PHY_XS, XGE_PHY_CONTROL) &
439 XGE_PHY_CONTROL_RESET);
443 format_ixge_rx_from_hw_descriptor (u8 * s, va_list * va)
445 ixge_rx_from_hw_descriptor_t *d =
446 va_arg (*va, ixge_rx_from_hw_descriptor_t *);
447 u32 s0 = d->status[0], s2 = d->status[2];
448 u32 is_ip4, is_ip6, is_ip, is_tcp, is_udp;
449 uword indent = format_get_indent (s);
451 s = format (s, "%s-owned",
452 (s2 & IXGE_RX_DESCRIPTOR_STATUS2_IS_OWNED_BY_SOFTWARE) ? "sw" :
455 format (s, ", length this descriptor %d, l3 offset %d",
456 d->n_packet_bytes_this_descriptor,
457 IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET (s0));
458 if (s2 & IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET)
459 s = format (s, ", end-of-packet");
461 s = format (s, "\n%U", format_white_space, indent);
463 if (s2 & IXGE_RX_DESCRIPTOR_STATUS2_ETHERNET_ERROR)
464 s = format (s, "layer2 error");
466 if (s0 & IXGE_RX_DESCRIPTOR_STATUS0_IS_LAYER2)
468 s = format (s, "layer 2 type %d", (s0 & 0x1f));
472 if (s2 & IXGE_RX_DESCRIPTOR_STATUS2_IS_VLAN)
473 s = format (s, "vlan header 0x%x\n%U", d->vlan_tag,
474 format_white_space, indent);
476 if ((is_ip4 = (s0 & IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4)))
478 s = format (s, "ip4%s",
479 (s0 & IXGE_RX_DESCRIPTOR_STATUS0_IS_IP4_EXT) ? " options" :
481 if (s2 & IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED)
482 s = format (s, " checksum %s",
483 (s2 & IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR) ?
486 if ((is_ip6 = (s0 & IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6)))
487 s = format (s, "ip6%s",
488 (s0 & IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6_EXT) ? " extended" :
491 if ((is_ip = (is_ip4 | is_ip6)))
493 is_tcp = (s0 & IXGE_RX_DESCRIPTOR_STATUS0_IS_TCP) != 0;
494 is_udp = (s0 & IXGE_RX_DESCRIPTOR_STATUS0_IS_UDP) != 0;
496 s = format (s, ", tcp");
498 s = format (s, ", udp");
501 if (s2 & IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED)
502 s = format (s, ", tcp checksum %s",
503 (s2 & IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR) ? "bad" :
505 if (s2 & IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED)
506 s = format (s, ", udp checksum %s",
507 (s2 & IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR) ? "bad" :
514 format_ixge_tx_descriptor (u8 * s, va_list * va)
516 ixge_tx_descriptor_t *d = va_arg (*va, ixge_tx_descriptor_t *);
517 u32 s0 = d->status0, s1 = d->status1;
518 uword indent = format_get_indent (s);
521 s = format (s, "buffer 0x%Lx, %d packet bytes, %d bytes this buffer",
522 d->buffer_address, s1 >> 14, d->n_bytes_this_buffer);
524 s = format (s, "\n%U", format_white_space, indent);
526 if ((v = (s0 >> 0) & 3))
527 s = format (s, "reserved 0x%x, ", v);
529 if ((v = (s0 >> 2) & 3))
530 s = format (s, "mac 0x%x, ", v);
532 if ((v = (s0 >> 4) & 0xf) != 3)
533 s = format (s, "type 0x%x, ", v);
535 s = format (s, "%s%s%s%s%s%s%s%s",
536 (s0 & (1 << 8)) ? "eop, " : "",
537 (s0 & (1 << 9)) ? "insert-fcs, " : "",
538 (s0 & (1 << 10)) ? "reserved26, " : "",
539 (s0 & (1 << 11)) ? "report-status, " : "",
540 (s0 & (1 << 12)) ? "reserved28, " : "",
541 (s0 & (1 << 13)) ? "is-advanced, " : "",
542 (s0 & (1 << 14)) ? "vlan-enable, " : "",
543 (s0 & (1 << 15)) ? "tx-segmentation, " : "");
545 if ((v = s1 & 0xf) != 0)
546 s = format (s, "status 0x%x, ", v);
548 if ((v = (s1 >> 4) & 0xf))
549 s = format (s, "context 0x%x, ", v);
551 if ((v = (s1 >> 8) & 0x3f))
552 s = format (s, "options 0x%x, ", v);
559 ixge_descriptor_t before, after;
567 u8 is_start_of_packet;
569 /* Copy of VLIB buffer; packet data stored in pre_data. */
570 vlib_buffer_t buffer;
571 } ixge_rx_dma_trace_t;
574 format_ixge_rx_dma_trace (u8 * s, va_list * va)
576 CLIB_UNUSED (vlib_main_t * vm) = va_arg (*va, vlib_main_t *);
577 vlib_node_t *node = va_arg (*va, vlib_node_t *);
578 vnet_main_t *vnm = vnet_get_main ();
579 ixge_rx_dma_trace_t *t = va_arg (*va, ixge_rx_dma_trace_t *);
580 ixge_main_t *xm = &ixge_main;
581 ixge_device_t *xd = vec_elt_at_index (xm->devices, t->device_index);
582 format_function_t *f;
583 uword indent = format_get_indent (s);
586 vnet_sw_interface_t *sw =
587 vnet_get_sw_interface (vnm, xd->vlib_sw_if_index);
589 format (s, "%U rx queue %d", format_vnet_sw_interface_name, vnm, sw,
593 s = format (s, "\n%Ubefore: %U",
594 format_white_space, indent,
595 format_ixge_rx_from_hw_descriptor, &t->before);
596 s = format (s, "\n%Uafter : head/tail address 0x%Lx/0x%Lx",
597 format_white_space, indent,
598 t->after.rx_to_hw.head_address, t->after.rx_to_hw.tail_address);
600 s = format (s, "\n%Ubuffer 0x%x: %U",
601 format_white_space, indent,
602 t->buffer_index, format_vlib_buffer, &t->buffer);
604 s = format (s, "\n%U", format_white_space, indent);
606 f = node->format_buffer;
607 if (!f || !t->is_start_of_packet)
608 f = format_hex_bytes;
609 s = format (s, "%U", f, t->buffer.pre_data, sizeof (t->buffer.pre_data));
614 #define foreach_ixge_error \
615 _ (none, "no error") \
616 _ (tx_full_drops, "tx ring full drops") \
617 _ (ip4_checksum_error, "ip4 checksum errors") \
618 _ (rx_alloc_fail, "rx buf alloc from free list failed") \
619 _ (rx_alloc_no_physmem, "rx buf alloc failed no physmem")
623 #define _(f,s) IXGE_ERROR_##f,
630 ixge_rx_next_and_error_from_status_x1 (ixge_device_t * xd,
632 u8 * next0, u8 * error0, u32 * flags0)
634 u8 is0_ip4, is0_ip6, n0, e0;
637 e0 = IXGE_ERROR_none;
638 n0 = IXGE_RX_NEXT_ETHERNET_INPUT;
640 is0_ip4 = s02 & IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED;
641 n0 = is0_ip4 ? IXGE_RX_NEXT_IP4_INPUT : n0;
643 e0 = (is0_ip4 && (s02 & IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR)
644 ? IXGE_ERROR_ip4_checksum_error : e0);
646 is0_ip6 = s00 & IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6;
647 n0 = is0_ip6 ? IXGE_RX_NEXT_IP6_INPUT : n0;
649 n0 = (xd->per_interface_next_index != ~0) ?
650 xd->per_interface_next_index : n0;
652 /* Check for error. */
653 n0 = e0 != IXGE_ERROR_none ? IXGE_RX_NEXT_DROP : n0;
655 f0 = ((s02 & (IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED
656 | IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED))
657 ? IP_BUFFER_L4_CHECKSUM_COMPUTED : 0);
659 f0 |= ((s02 & (IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR
660 | IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR))
661 ? 0 : IP_BUFFER_L4_CHECKSUM_CORRECT);
669 ixge_rx_next_and_error_from_status_x2 (ixge_device_t * xd,
672 u8 * next0, u8 * error0, u32 * flags0,
673 u8 * next1, u8 * error1, u32 * flags1)
675 u8 is0_ip4, is0_ip6, n0, e0;
676 u8 is1_ip4, is1_ip6, n1, e1;
679 e0 = e1 = IXGE_ERROR_none;
680 n0 = n1 = IXGE_RX_NEXT_IP4_INPUT;
682 is0_ip4 = s02 & IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED;
683 is1_ip4 = s12 & IXGE_RX_DESCRIPTOR_STATUS2_IS_IP4_CHECKSUMMED;
685 n0 = is0_ip4 ? IXGE_RX_NEXT_IP4_INPUT : n0;
686 n1 = is1_ip4 ? IXGE_RX_NEXT_IP4_INPUT : n1;
688 e0 = (is0_ip4 && (s02 & IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR)
689 ? IXGE_ERROR_ip4_checksum_error : e0);
690 e1 = (is1_ip4 && (s12 & IXGE_RX_DESCRIPTOR_STATUS2_IP4_CHECKSUM_ERROR)
691 ? IXGE_ERROR_ip4_checksum_error : e1);
693 is0_ip6 = s00 & IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6;
694 is1_ip6 = s10 & IXGE_RX_DESCRIPTOR_STATUS0_IS_IP6;
696 n0 = is0_ip6 ? IXGE_RX_NEXT_IP6_INPUT : n0;
697 n1 = is1_ip6 ? IXGE_RX_NEXT_IP6_INPUT : n1;
699 n0 = (xd->per_interface_next_index != ~0) ?
700 xd->per_interface_next_index : n0;
701 n1 = (xd->per_interface_next_index != ~0) ?
702 xd->per_interface_next_index : n1;
704 /* Check for error. */
705 n0 = e0 != IXGE_ERROR_none ? IXGE_RX_NEXT_DROP : n0;
706 n1 = e1 != IXGE_ERROR_none ? IXGE_RX_NEXT_DROP : n1;
714 f0 = ((s02 & (IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED
715 | IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED))
716 ? IP_BUFFER_L4_CHECKSUM_COMPUTED : 0);
717 f1 = ((s12 & (IXGE_RX_DESCRIPTOR_STATUS2_IS_TCP_CHECKSUMMED
718 | IXGE_RX_DESCRIPTOR_STATUS2_IS_UDP_CHECKSUMMED))
719 ? IP_BUFFER_L4_CHECKSUM_COMPUTED : 0);
721 f0 |= ((s02 & (IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR
722 | IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR))
723 ? 0 : IP_BUFFER_L4_CHECKSUM_CORRECT);
724 f1 |= ((s12 & (IXGE_RX_DESCRIPTOR_STATUS2_TCP_CHECKSUM_ERROR
725 | IXGE_RX_DESCRIPTOR_STATUS2_UDP_CHECKSUM_ERROR))
726 ? 0 : IP_BUFFER_L4_CHECKSUM_CORRECT);
733 ixge_rx_trace (ixge_main_t * xm,
735 ixge_dma_queue_t * dq,
736 ixge_descriptor_t * before_descriptors,
737 u32 * before_buffers,
738 ixge_descriptor_t * after_descriptors, uword n_descriptors)
740 vlib_main_t *vm = xm->vlib_main;
741 vlib_node_runtime_t *node = dq->rx.node;
742 ixge_rx_from_hw_descriptor_t *bd;
743 ixge_rx_to_hw_descriptor_t *ad;
744 u32 *b, n_left, is_sop, next_index_sop;
746 n_left = n_descriptors;
748 bd = &before_descriptors->rx_from_hw;
749 ad = &after_descriptors->rx_to_hw;
750 is_sop = dq->rx.is_start_of_packet;
751 next_index_sop = dq->rx.saved_start_of_packet_next_index;
755 u32 bi0, bi1, flags0, flags1;
756 vlib_buffer_t *b0, *b1;
757 ixge_rx_dma_trace_t *t0, *t1;
758 u8 next0, error0, next1, error1;
764 b0 = vlib_get_buffer (vm, bi0);
765 b1 = vlib_get_buffer (vm, bi1);
767 ixge_rx_next_and_error_from_status_x2 (xd,
768 bd[0].status[0], bd[0].status[2],
769 bd[1].status[0], bd[1].status[2],
770 &next0, &error0, &flags0,
771 &next1, &error1, &flags1);
773 next_index_sop = is_sop ? next0 : next_index_sop;
774 vlib_trace_buffer (vm, node, next_index_sop, b0, /* follow_chain */ 0);
775 t0 = vlib_add_trace (vm, node, b0, sizeof (t0[0]));
776 t0->is_start_of_packet = is_sop;
777 is_sop = (b0->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
779 next_index_sop = is_sop ? next1 : next_index_sop;
780 vlib_trace_buffer (vm, node, next_index_sop, b1, /* follow_chain */ 0);
781 t1 = vlib_add_trace (vm, node, b1, sizeof (t1[0]));
782 t1->is_start_of_packet = is_sop;
783 is_sop = (b1->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
785 t0->queue_index = dq->queue_index;
786 t1->queue_index = dq->queue_index;
787 t0->device_index = xd->device_index;
788 t1->device_index = xd->device_index;
789 t0->before.rx_from_hw = bd[0];
790 t1->before.rx_from_hw = bd[1];
791 t0->after.rx_to_hw = ad[0];
792 t1->after.rx_to_hw = ad[1];
793 t0->buffer_index = bi0;
794 t1->buffer_index = bi1;
795 memcpy (&t0->buffer, b0, sizeof (b0[0]) - sizeof (b0->pre_data));
796 memcpy (&t1->buffer, b1, sizeof (b1[0]) - sizeof (b0->pre_data));
797 memcpy (t0->buffer.pre_data, b0->data + b0->current_data,
798 sizeof (t0->buffer.pre_data));
799 memcpy (t1->buffer.pre_data, b1->data + b1->current_data,
800 sizeof (t1->buffer.pre_data));
811 ixge_rx_dma_trace_t *t0;
817 b0 = vlib_get_buffer (vm, bi0);
819 ixge_rx_next_and_error_from_status_x1 (xd,
820 bd[0].status[0], bd[0].status[2],
821 &next0, &error0, &flags0);
823 next_index_sop = is_sop ? next0 : next_index_sop;
824 vlib_trace_buffer (vm, node, next_index_sop, b0, /* follow_chain */ 0);
825 t0 = vlib_add_trace (vm, node, b0, sizeof (t0[0]));
826 t0->is_start_of_packet = is_sop;
827 is_sop = (b0->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
829 t0->queue_index = dq->queue_index;
830 t0->device_index = xd->device_index;
831 t0->before.rx_from_hw = bd[0];
832 t0->after.rx_to_hw = ad[0];
833 t0->buffer_index = bi0;
834 memcpy (&t0->buffer, b0, sizeof (b0[0]) - sizeof (b0->pre_data));
835 memcpy (t0->buffer.pre_data, b0->data + b0->current_data,
836 sizeof (t0->buffer.pre_data));
846 ixge_tx_descriptor_t descriptor;
854 u8 is_start_of_packet;
856 /* Copy of VLIB buffer; packet data stored in pre_data. */
857 vlib_buffer_t buffer;
858 } ixge_tx_dma_trace_t;
861 format_ixge_tx_dma_trace (u8 * s, va_list * va)
863 CLIB_UNUSED (vlib_main_t * vm) = va_arg (*va, vlib_main_t *);
864 CLIB_UNUSED (vlib_node_t * node) = va_arg (*va, vlib_node_t *);
865 ixge_tx_dma_trace_t *t = va_arg (*va, ixge_tx_dma_trace_t *);
866 vnet_main_t *vnm = vnet_get_main ();
867 ixge_main_t *xm = &ixge_main;
868 ixge_device_t *xd = vec_elt_at_index (xm->devices, t->device_index);
869 format_function_t *f;
870 uword indent = format_get_indent (s);
873 vnet_sw_interface_t *sw =
874 vnet_get_sw_interface (vnm, xd->vlib_sw_if_index);
876 format (s, "%U tx queue %d", format_vnet_sw_interface_name, vnm, sw,
880 s = format (s, "\n%Udescriptor: %U",
881 format_white_space, indent,
882 format_ixge_tx_descriptor, &t->descriptor);
884 s = format (s, "\n%Ubuffer 0x%x: %U",
885 format_white_space, indent,
886 t->buffer_index, format_vlib_buffer, &t->buffer);
888 s = format (s, "\n%U", format_white_space, indent);
890 f = format_ethernet_header_with_length;
891 if (!f || !t->is_start_of_packet)
892 f = format_hex_bytes;
893 s = format (s, "%U", f, t->buffer.pre_data, sizeof (t->buffer.pre_data));
900 vlib_node_runtime_t *node;
902 u32 is_start_of_packet;
904 u32 n_bytes_in_packet;
906 ixge_tx_descriptor_t *start_of_packet_descriptor;
910 ixge_tx_trace (ixge_main_t * xm,
912 ixge_dma_queue_t * dq,
913 ixge_tx_state_t * tx_state,
914 ixge_tx_descriptor_t * descriptors,
915 u32 * buffers, uword n_descriptors)
917 vlib_main_t *vm = xm->vlib_main;
918 vlib_node_runtime_t *node = tx_state->node;
919 ixge_tx_descriptor_t *d;
920 u32 *b, n_left, is_sop;
922 n_left = n_descriptors;
925 is_sop = tx_state->is_start_of_packet;
930 vlib_buffer_t *b0, *b1;
931 ixge_tx_dma_trace_t *t0, *t1;
937 b0 = vlib_get_buffer (vm, bi0);
938 b1 = vlib_get_buffer (vm, bi1);
940 t0 = vlib_add_trace (vm, node, b0, sizeof (t0[0]));
941 t0->is_start_of_packet = is_sop;
942 is_sop = (b0->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
944 t1 = vlib_add_trace (vm, node, b1, sizeof (t1[0]));
945 t1->is_start_of_packet = is_sop;
946 is_sop = (b1->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
948 t0->queue_index = dq->queue_index;
949 t1->queue_index = dq->queue_index;
950 t0->device_index = xd->device_index;
951 t1->device_index = xd->device_index;
952 t0->descriptor = d[0];
953 t1->descriptor = d[1];
954 t0->buffer_index = bi0;
955 t1->buffer_index = bi1;
956 memcpy (&t0->buffer, b0, sizeof (b0[0]) - sizeof (b0->pre_data));
957 memcpy (&t1->buffer, b1, sizeof (b1[0]) - sizeof (b0->pre_data));
958 memcpy (t0->buffer.pre_data, b0->data + b0->current_data,
959 sizeof (t0->buffer.pre_data));
960 memcpy (t1->buffer.pre_data, b1->data + b1->current_data,
961 sizeof (t1->buffer.pre_data));
971 ixge_tx_dma_trace_t *t0;
976 b0 = vlib_get_buffer (vm, bi0);
978 t0 = vlib_add_trace (vm, node, b0, sizeof (t0[0]));
979 t0->is_start_of_packet = is_sop;
980 is_sop = (b0->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
982 t0->queue_index = dq->queue_index;
983 t0->device_index = xd->device_index;
984 t0->descriptor = d[0];
985 t0->buffer_index = bi0;
986 memcpy (&t0->buffer, b0, sizeof (b0[0]) - sizeof (b0->pre_data));
987 memcpy (t0->buffer.pre_data, b0->data + b0->current_data,
988 sizeof (t0->buffer.pre_data));
996 ixge_ring_sub (ixge_dma_queue_t * q, u32 i0, u32 i1)
999 ASSERT (i0 < q->n_descriptors);
1000 ASSERT (i1 < q->n_descriptors);
1001 return d < 0 ? q->n_descriptors + d : d;
1005 ixge_ring_add (ixge_dma_queue_t * q, u32 i0, u32 i1)
1008 ASSERT (i0 < q->n_descriptors);
1009 ASSERT (i1 < q->n_descriptors);
1010 d -= d >= q->n_descriptors ? q->n_descriptors : 0;
1015 ixge_tx_descriptor_matches_template (ixge_main_t * xm,
1016 ixge_tx_descriptor_t * d)
1020 cmp = ((d->status0 & xm->tx_descriptor_template_mask.status0)
1021 ^ xm->tx_descriptor_template.status0);
1024 cmp = ((d->status1 & xm->tx_descriptor_template_mask.status1)
1025 ^ xm->tx_descriptor_template.status1);
1033 ixge_tx_no_wrap (ixge_main_t * xm,
1035 ixge_dma_queue_t * dq,
1037 u32 start_descriptor_index,
1038 u32 n_descriptors, ixge_tx_state_t * tx_state)
1040 vlib_main_t *vm = xm->vlib_main;
1041 ixge_tx_descriptor_t *d, *d_sop;
1042 u32 n_left = n_descriptors;
1043 u32 *to_free = vec_end (xm->tx_buffers_pending_free);
1045 vec_elt_at_index (dq->descriptor_buffer_indices, start_descriptor_index);
1046 u32 is_sop = tx_state->is_start_of_packet;
1047 u32 len_sop = tx_state->n_bytes_in_packet;
1048 u16 template_status = xm->tx_descriptor_template.status0;
1049 u32 descriptor_prefetch_rotor = 0;
1051 ASSERT (start_descriptor_index + n_descriptors <= dq->n_descriptors);
1052 d = &dq->descriptors[start_descriptor_index].tx;
1053 d_sop = is_sop ? d : tx_state->start_of_packet_descriptor;
1057 vlib_buffer_t *b0, *b1;
1060 u8 is_eop0, is_eop1;
1062 /* Prefetch next iteration. */
1063 vlib_prefetch_buffer_with_index (vm, buffers[2], LOAD);
1064 vlib_prefetch_buffer_with_index (vm, buffers[3], LOAD);
1066 if ((descriptor_prefetch_rotor & 0x3) == 0)
1067 CLIB_PREFETCH (d + 4, CLIB_CACHE_LINE_BYTES, STORE);
1069 descriptor_prefetch_rotor += 2;
1074 to_free[0] = fi0 = to_tx[0];
1076 to_free += fi0 != 0;
1078 to_free[0] = fi1 = to_tx[1];
1080 to_free += fi1 != 0;
1086 b0 = vlib_get_buffer (vm, bi0);
1087 b1 = vlib_get_buffer (vm, bi1);
1089 is_eop0 = (b0->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
1090 is_eop1 = (b1->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
1092 len0 = b0->current_length;
1093 len1 = b1->current_length;
1095 ASSERT (ixge_tx_descriptor_matches_template (xm, d + 0));
1096 ASSERT (ixge_tx_descriptor_matches_template (xm, d + 1));
1098 d[0].buffer_address =
1099 vlib_get_buffer_data_physical_address (vm, bi0) + b0->current_data;
1100 d[1].buffer_address =
1101 vlib_get_buffer_data_physical_address (vm, bi1) + b1->current_data;
1103 d[0].n_bytes_this_buffer = len0;
1104 d[1].n_bytes_this_buffer = len1;
1107 template_status | (is_eop0 <<
1108 IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET);
1110 template_status | (is_eop1 <<
1111 IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET);
1113 len_sop = (is_sop ? 0 : len_sop) + len0;
1115 IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET (len_sop);
1117 d_sop = is_eop0 ? d : d_sop;
1121 len_sop = (is_sop ? 0 : len_sop) + len1;
1123 IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET (len_sop);
1125 d_sop = is_eop1 ? d : d_sop;
1138 to_free[0] = fi0 = to_tx[0];
1140 to_free += fi0 != 0;
1146 b0 = vlib_get_buffer (vm, bi0);
1148 is_eop0 = (b0->flags & VLIB_BUFFER_NEXT_PRESENT) == 0;
1150 len0 = b0->current_length;
1152 ASSERT (ixge_tx_descriptor_matches_template (xm, d + 0));
1154 d[0].buffer_address =
1155 vlib_get_buffer_data_physical_address (vm, bi0) + b0->current_data;
1157 d[0].n_bytes_this_buffer = len0;
1160 template_status | (is_eop0 <<
1161 IXGE_TX_DESCRIPTOR_STATUS0_LOG2_IS_END_OF_PACKET);
1163 len_sop = (is_sop ? 0 : len_sop) + len0;
1165 IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET (len_sop);
1167 d_sop = is_eop0 ? d : d_sop;
1172 if (tx_state->node->flags & VLIB_NODE_FLAG_TRACE)
1175 vec_elt_at_index (dq->descriptor_buffer_indices,
1176 start_descriptor_index);
1177 ixge_tx_trace (xm, xd, dq, tx_state,
1178 &dq->descriptors[start_descriptor_index].tx, to_tx,
1182 _vec_len (xm->tx_buffers_pending_free) =
1183 to_free - xm->tx_buffers_pending_free;
1185 /* When we are done d_sop can point to end of ring. Wrap it if so. */
1187 ixge_tx_descriptor_t *d_start = &dq->descriptors[0].tx;
1189 ASSERT (d_sop - d_start <= dq->n_descriptors);
1190 d_sop = d_sop - d_start == dq->n_descriptors ? d_start : d_sop;
1193 tx_state->is_start_of_packet = is_sop;
1194 tx_state->start_of_packet_descriptor = d_sop;
1195 tx_state->n_bytes_in_packet = len_sop;
1197 return n_descriptors;
1201 ixge_interface_tx (vlib_main_t * vm,
1202 vlib_node_runtime_t * node, vlib_frame_t * f)
1204 ixge_main_t *xm = &ixge_main;
1205 vnet_interface_output_runtime_t *rd = (void *) node->runtime_data;
1206 ixge_device_t *xd = vec_elt_at_index (xm->devices, rd->dev_instance);
1207 ixge_dma_queue_t *dq;
1208 u32 *from, n_left_tx, n_descriptors_to_tx, n_tail_drop;
1209 u32 queue_index = 0; /* fixme parameter */
1210 ixge_tx_state_t tx_state;
1212 tx_state.node = node;
1213 tx_state.is_start_of_packet = 1;
1214 tx_state.start_of_packet_descriptor = 0;
1215 tx_state.n_bytes_in_packet = 0;
1217 from = vlib_frame_vector_args (f);
1219 dq = vec_elt_at_index (xd->dma_queues[VLIB_TX], queue_index);
1221 dq->head_index = dq->tx.head_index_write_back[0];
1223 /* Since head == tail means ring is empty we can send up to dq->n_descriptors - 1. */
1224 n_left_tx = dq->n_descriptors - 1;
1225 n_left_tx -= ixge_ring_sub (dq, dq->head_index, dq->tail_index);
1227 _vec_len (xm->tx_buffers_pending_free) = 0;
1229 n_descriptors_to_tx = f->n_vectors;
1231 if (PREDICT_FALSE (n_descriptors_to_tx > n_left_tx))
1233 i32 i, n_ok, i_eop, i_sop;
1236 for (i = n_left_tx - 1; i >= 0; i--)
1238 vlib_buffer_t *b = vlib_get_buffer (vm, from[i]);
1239 if (!(b->flags & VLIB_BUFFER_NEXT_PRESENT))
1241 if (i_sop != ~0 && i_eop != ~0)
1253 ELOG_TYPE_DECLARE (e) =
1255 .function = (char *) __FUNCTION__,.format =
1256 "ixge %d, ring full to tx %d head %d tail %d",.format_args =
1260 u16 instance, to_tx, head, tail;
1262 ed = ELOG_DATA (&vm->elog_main, e);
1263 ed->instance = xd->device_index;
1264 ed->to_tx = n_descriptors_to_tx;
1265 ed->head = dq->head_index;
1266 ed->tail = dq->tail_index;
1269 if (n_ok < n_descriptors_to_tx)
1271 n_tail_drop = n_descriptors_to_tx - n_ok;
1272 vec_add (xm->tx_buffers_pending_free, from + n_ok, n_tail_drop);
1273 vlib_error_count (vm, ixge_input_node.index,
1274 IXGE_ERROR_tx_full_drops, n_tail_drop);
1277 n_descriptors_to_tx = n_ok;
1280 dq->tx.n_buffers_on_ring += n_descriptors_to_tx;
1282 /* Process from tail to end of descriptor ring. */
1283 if (n_descriptors_to_tx > 0 && dq->tail_index < dq->n_descriptors)
1286 clib_min (dq->n_descriptors - dq->tail_index, n_descriptors_to_tx);
1287 n = ixge_tx_no_wrap (xm, xd, dq, from, dq->tail_index, n, &tx_state);
1289 n_descriptors_to_tx -= n;
1290 dq->tail_index += n;
1291 ASSERT (dq->tail_index <= dq->n_descriptors);
1292 if (dq->tail_index == dq->n_descriptors)
1296 if (n_descriptors_to_tx > 0)
1299 ixge_tx_no_wrap (xm, xd, dq, from, 0, n_descriptors_to_tx, &tx_state);
1301 ASSERT (n == n_descriptors_to_tx);
1302 dq->tail_index += n;
1303 ASSERT (dq->tail_index <= dq->n_descriptors);
1304 if (dq->tail_index == dq->n_descriptors)
1308 /* We should only get full packets. */
1309 ASSERT (tx_state.is_start_of_packet);
1311 /* Report status when last descriptor is done. */
1313 u32 i = dq->tail_index == 0 ? dq->n_descriptors - 1 : dq->tail_index - 1;
1314 ixge_tx_descriptor_t *d = &dq->descriptors[i].tx;
1315 d->status0 |= IXGE_TX_DESCRIPTOR_STATUS0_REPORT_STATUS;
1318 /* Give new descriptors to hardware. */
1320 ixge_dma_regs_t *dr = get_dma_regs (xd, VLIB_TX, queue_index);
1322 CLIB_MEMORY_BARRIER ();
1324 dr->tail_index = dq->tail_index;
1327 /* Free any buffers that are done. */
1329 u32 n = _vec_len (xm->tx_buffers_pending_free);
1332 vlib_buffer_free_no_next (vm, xm->tx_buffers_pending_free, n);
1333 _vec_len (xm->tx_buffers_pending_free) = 0;
1334 ASSERT (dq->tx.n_buffers_on_ring >= n);
1335 dq->tx.n_buffers_on_ring -= (n - n_tail_drop);
1339 return f->n_vectors;
1343 ixge_rx_queue_no_wrap (ixge_main_t * xm,
1345 ixge_dma_queue_t * dq,
1346 u32 start_descriptor_index, u32 n_descriptors)
1348 vlib_main_t *vm = xm->vlib_main;
1349 vlib_node_runtime_t *node = dq->rx.node;
1350 ixge_descriptor_t *d;
1351 static ixge_descriptor_t *d_trace_save;
1352 static u32 *d_trace_buffers;
1353 u32 n_descriptors_left = n_descriptors;
1355 vec_elt_at_index (dq->descriptor_buffer_indices, start_descriptor_index);
1357 u32 bi_sop = dq->rx.saved_start_of_packet_buffer_index;
1358 u32 bi_last = dq->rx.saved_last_buffer_index;
1359 u32 next_index_sop = dq->rx.saved_start_of_packet_next_index;
1360 u32 is_sop = dq->rx.is_start_of_packet;
1361 u32 next_index, n_left_to_next, *to_next;
1364 u32 n_trace = vlib_get_trace_count (vm, node);
1365 vlib_buffer_t *b_last, b_dummy;
1367 ASSERT (start_descriptor_index + n_descriptors <= dq->n_descriptors);
1368 d = &dq->descriptors[start_descriptor_index];
1370 b_last = bi_last != ~0 ? vlib_get_buffer (vm, bi_last) : &b_dummy;
1371 next_index = dq->rx.next_index;
1375 u32 n = clib_min (n_trace, n_descriptors);
1378 _vec_len (d_trace_save) = 0;
1379 _vec_len (d_trace_buffers) = 0;
1381 vec_add (d_trace_save, (ixge_descriptor_t *) d, n);
1382 vec_add (d_trace_buffers, to_rx, n);
1386 uword l = vec_len (xm->rx_buffers_to_add);
1388 if (l < n_descriptors_left)
1390 u32 n_to_alloc = 2 * dq->n_descriptors - l;
1393 vec_resize (xm->rx_buffers_to_add, n_to_alloc);
1395 _vec_len (xm->rx_buffers_to_add) = l;
1396 n_allocated = vlib_buffer_alloc_from_free_list
1397 (vm, xm->rx_buffers_to_add + l, n_to_alloc,
1398 xm->vlib_buffer_free_list_index);
1399 _vec_len (xm->rx_buffers_to_add) += n_allocated;
1401 /* Handle transient allocation failure */
1402 if (PREDICT_FALSE (l + n_allocated <= n_descriptors_left))
1404 if (n_allocated == 0)
1405 vlib_error_count (vm, ixge_input_node.index,
1406 IXGE_ERROR_rx_alloc_no_physmem, 1);
1408 vlib_error_count (vm, ixge_input_node.index,
1409 IXGE_ERROR_rx_alloc_fail, 1);
1411 n_descriptors_left = l + n_allocated;
1413 n_descriptors = n_descriptors_left;
1416 /* Add buffers from end of vector going backwards. */
1417 to_add = vec_end (xm->rx_buffers_to_add) - 1;
1420 while (n_descriptors_left > 0)
1422 vlib_get_next_frame (vm, node, next_index, to_next, n_left_to_next);
1424 while (n_descriptors_left >= 4 && n_left_to_next >= 2)
1426 vlib_buffer_t *b0, *b1;
1427 u32 bi0, fi0, len0, l3_offset0, s20, s00, flags0;
1428 u32 bi1, fi1, len1, l3_offset1, s21, s01, flags1;
1429 u8 is_eop0, error0, next0;
1430 u8 is_eop1, error1, next1;
1431 ixge_descriptor_t d0, d1;
1433 vlib_prefetch_buffer_with_index (vm, to_rx[2], STORE);
1434 vlib_prefetch_buffer_with_index (vm, to_rx[3], STORE);
1436 CLIB_PREFETCH (d + 2, 32, STORE);
1438 d0.as_u32x4 = d[0].as_u32x4;
1439 d1.as_u32x4 = d[1].as_u32x4;
1441 s20 = d0.rx_from_hw.status[2];
1442 s21 = d1.rx_from_hw.status[2];
1444 s00 = d0.rx_from_hw.status[0];
1445 s01 = d1.rx_from_hw.status[0];
1448 ((s20 & s21) & IXGE_RX_DESCRIPTOR_STATUS2_IS_OWNED_BY_SOFTWARE))
1449 goto found_hw_owned_descriptor_x2;
1454 ASSERT (to_add - 1 >= xm->rx_buffers_to_add);
1463 ASSERT (VLIB_BUFFER_KNOWN_ALLOCATED ==
1464 vlib_buffer_is_known (vm, bi0));
1465 ASSERT (VLIB_BUFFER_KNOWN_ALLOCATED ==
1466 vlib_buffer_is_known (vm, bi1));
1467 ASSERT (VLIB_BUFFER_KNOWN_ALLOCATED ==
1468 vlib_buffer_is_known (vm, fi0));
1469 ASSERT (VLIB_BUFFER_KNOWN_ALLOCATED ==
1470 vlib_buffer_is_known (vm, fi1));
1472 b0 = vlib_get_buffer (vm, bi0);
1473 b1 = vlib_get_buffer (vm, bi1);
1476 * Turn this on if you run into
1477 * "bad monkey" contexts, and you want to know exactly
1478 * which nodes they've visited... See main.c...
1480 VLIB_BUFFER_TRACE_TRAJECTORY_INIT (b0);
1481 VLIB_BUFFER_TRACE_TRAJECTORY_INIT (b1);
1483 CLIB_PREFETCH (b0->data, CLIB_CACHE_LINE_BYTES, LOAD);
1484 CLIB_PREFETCH (b1->data, CLIB_CACHE_LINE_BYTES, LOAD);
1486 is_eop0 = (s20 & IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET) != 0;
1487 is_eop1 = (s21 & IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET) != 0;
1489 ixge_rx_next_and_error_from_status_x2 (xd, s00, s20, s01, s21,
1490 &next0, &error0, &flags0,
1491 &next1, &error1, &flags1);
1493 next0 = is_sop ? next0 : next_index_sop;
1494 next1 = is_eop0 ? next1 : next0;
1495 next_index_sop = next1;
1497 b0->flags |= flags0 | (!is_eop0 << VLIB_BUFFER_LOG2_NEXT_PRESENT);
1498 b1->flags |= flags1 | (!is_eop1 << VLIB_BUFFER_LOG2_NEXT_PRESENT);
1500 vnet_buffer (b0)->sw_if_index[VLIB_RX] = xd->vlib_sw_if_index;
1501 vnet_buffer (b1)->sw_if_index[VLIB_RX] = xd->vlib_sw_if_index;
1502 vnet_buffer (b0)->sw_if_index[VLIB_TX] = (u32) ~ 0;
1503 vnet_buffer (b1)->sw_if_index[VLIB_TX] = (u32) ~ 0;
1505 b0->error = node->errors[error0];
1506 b1->error = node->errors[error1];
1508 len0 = d0.rx_from_hw.n_packet_bytes_this_descriptor;
1509 len1 = d1.rx_from_hw.n_packet_bytes_this_descriptor;
1510 n_bytes += len0 + len1;
1511 n_packets += is_eop0 + is_eop1;
1513 /* Give new buffers to hardware. */
1514 d0.rx_to_hw.tail_address =
1515 vlib_get_buffer_data_physical_address (vm, fi0);
1516 d1.rx_to_hw.tail_address =
1517 vlib_get_buffer_data_physical_address (vm, fi1);
1518 d0.rx_to_hw.head_address = d[0].rx_to_hw.tail_address;
1519 d1.rx_to_hw.head_address = d[1].rx_to_hw.tail_address;
1520 d[0].as_u32x4 = d0.as_u32x4;
1521 d[1].as_u32x4 = d1.as_u32x4;
1524 n_descriptors_left -= 2;
1526 /* Point to either l2 or l3 header depending on next. */
1527 l3_offset0 = (is_sop && (next0 != IXGE_RX_NEXT_ETHERNET_INPUT))
1528 ? IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET (s00) : 0;
1529 l3_offset1 = (is_eop0 && (next1 != IXGE_RX_NEXT_ETHERNET_INPUT))
1530 ? IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET (s01) : 0;
1532 b0->current_length = len0 - l3_offset0;
1533 b1->current_length = len1 - l3_offset1;
1534 b0->current_data = l3_offset0;
1535 b1->current_data = l3_offset1;
1537 b_last->next_buffer = is_sop ? ~0 : bi0;
1538 b0->next_buffer = is_eop0 ? ~0 : bi1;
1544 u32 bi_sop0 = is_sop ? bi0 : bi_sop;
1545 u32 bi_sop1 = is_eop0 ? bi1 : bi_sop0;
1549 u8 *msg = vlib_validate_buffer (vm, bi_sop0,
1550 /* follow_buffer_next */ 1);
1555 u8 *msg = vlib_validate_buffer (vm, bi_sop1,
1556 /* follow_buffer_next */ 1);
1560 if (0) /* "Dave" version */
1562 u32 bi_sop0 = is_sop ? bi0 : bi_sop;
1563 u32 bi_sop1 = is_eop0 ? bi1 : bi_sop0;
1567 to_next[0] = bi_sop0;
1571 vlib_validate_buffer_enqueue_x1 (vm, node, next_index,
1572 to_next, n_left_to_next,
1577 to_next[0] = bi_sop1;
1581 vlib_validate_buffer_enqueue_x1 (vm, node, next_index,
1582 to_next, n_left_to_next,
1588 if (1) /* "Eliot" version */
1590 /* Speculatively enqueue to cached next. */
1591 u8 saved_is_sop = is_sop;
1592 u32 bi_sop_save = bi_sop;
1594 bi_sop = saved_is_sop ? bi0 : bi_sop;
1595 to_next[0] = bi_sop;
1597 n_left_to_next -= is_eop0;
1599 bi_sop = is_eop0 ? bi1 : bi_sop;
1600 to_next[0] = bi_sop;
1602 n_left_to_next -= is_eop1;
1607 (!(next0 == next_index && next1 == next_index)))
1609 /* Undo speculation. */
1610 to_next -= is_eop0 + is_eop1;
1611 n_left_to_next += is_eop0 + is_eop1;
1613 /* Re-do both descriptors being careful about where we enqueue. */
1614 bi_sop = saved_is_sop ? bi0 : bi_sop_save;
1617 if (next0 != next_index)
1618 vlib_set_next_frame_buffer (vm, node, next0, bi_sop);
1621 to_next[0] = bi_sop;
1623 n_left_to_next -= 1;
1627 bi_sop = is_eop0 ? bi1 : bi_sop;
1630 if (next1 != next_index)
1631 vlib_set_next_frame_buffer (vm, node, next1, bi_sop);
1634 to_next[0] = bi_sop;
1636 n_left_to_next -= 1;
1640 /* Switch cached next index when next for both packets is the same. */
1641 if (is_eop0 && is_eop1 && next0 == next1)
1643 vlib_put_next_frame (vm, node, next_index,
1646 vlib_get_next_frame (vm, node, next_index,
1647 to_next, n_left_to_next);
1653 /* Bail out of dual loop and proceed with single loop. */
1654 found_hw_owned_descriptor_x2:
1656 while (n_descriptors_left > 0 && n_left_to_next > 0)
1659 u32 bi0, fi0, len0, l3_offset0, s20, s00, flags0;
1660 u8 is_eop0, error0, next0;
1661 ixge_descriptor_t d0;
1663 d0.as_u32x4 = d[0].as_u32x4;
1665 s20 = d0.rx_from_hw.status[2];
1666 s00 = d0.rx_from_hw.status[0];
1668 if (!(s20 & IXGE_RX_DESCRIPTOR_STATUS2_IS_OWNED_BY_SOFTWARE))
1669 goto found_hw_owned_descriptor_x1;
1672 ASSERT (to_add >= xm->rx_buffers_to_add);
1679 ASSERT (VLIB_BUFFER_KNOWN_ALLOCATED ==
1680 vlib_buffer_is_known (vm, bi0));
1681 ASSERT (VLIB_BUFFER_KNOWN_ALLOCATED ==
1682 vlib_buffer_is_known (vm, fi0));
1684 b0 = vlib_get_buffer (vm, bi0);
1687 * Turn this on if you run into
1688 * "bad monkey" contexts, and you want to know exactly
1689 * which nodes they've visited...
1691 VLIB_BUFFER_TRACE_TRAJECTORY_INIT (b0);
1693 is_eop0 = (s20 & IXGE_RX_DESCRIPTOR_STATUS2_IS_END_OF_PACKET) != 0;
1694 ixge_rx_next_and_error_from_status_x1
1695 (xd, s00, s20, &next0, &error0, &flags0);
1697 next0 = is_sop ? next0 : next_index_sop;
1698 next_index_sop = next0;
1700 b0->flags |= flags0 | (!is_eop0 << VLIB_BUFFER_LOG2_NEXT_PRESENT);
1702 vnet_buffer (b0)->sw_if_index[VLIB_RX] = xd->vlib_sw_if_index;
1703 vnet_buffer (b0)->sw_if_index[VLIB_TX] = (u32) ~ 0;
1705 b0->error = node->errors[error0];
1707 len0 = d0.rx_from_hw.n_packet_bytes_this_descriptor;
1709 n_packets += is_eop0;
1711 /* Give new buffer to hardware. */
1712 d0.rx_to_hw.tail_address =
1713 vlib_get_buffer_data_physical_address (vm, fi0);
1714 d0.rx_to_hw.head_address = d0.rx_to_hw.tail_address;
1715 d[0].as_u32x4 = d0.as_u32x4;
1718 n_descriptors_left -= 1;
1720 /* Point to either l2 or l3 header depending on next. */
1721 l3_offset0 = (is_sop && (next0 != IXGE_RX_NEXT_ETHERNET_INPUT))
1722 ? IXGE_RX_DESCRIPTOR_STATUS0_L3_OFFSET (s00) : 0;
1723 b0->current_length = len0 - l3_offset0;
1724 b0->current_data = l3_offset0;
1726 b_last->next_buffer = is_sop ? ~0 : bi0;
1730 bi_sop = is_sop ? bi0 : bi_sop;
1732 if (CLIB_DEBUG > 0 && is_eop0)
1735 vlib_validate_buffer (vm, bi_sop, /* follow_buffer_next */ 1);
1739 if (0) /* "Dave" version */
1743 to_next[0] = bi_sop;
1747 vlib_validate_buffer_enqueue_x1 (vm, node, next_index,
1748 to_next, n_left_to_next,
1752 if (1) /* "Eliot" version */
1754 if (PREDICT_TRUE (next0 == next_index))
1756 to_next[0] = bi_sop;
1758 n_left_to_next -= is_eop0;
1762 if (next0 != next_index && is_eop0)
1763 vlib_set_next_frame_buffer (vm, node, next0, bi_sop);
1765 vlib_put_next_frame (vm, node, next_index, n_left_to_next);
1767 vlib_get_next_frame (vm, node, next_index,
1768 to_next, n_left_to_next);
1773 vlib_put_next_frame (vm, node, next_index, n_left_to_next);
1776 found_hw_owned_descriptor_x1:
1777 if (n_descriptors_left > 0)
1778 vlib_put_next_frame (vm, node, next_index, n_left_to_next);
1780 _vec_len (xm->rx_buffers_to_add) = (to_add + 1) - xm->rx_buffers_to_add;
1783 u32 n_done = n_descriptors - n_descriptors_left;
1785 if (n_trace > 0 && n_done > 0)
1787 u32 n = clib_min (n_trace, n_done);
1788 ixge_rx_trace (xm, xd, dq,
1791 &dq->descriptors[start_descriptor_index], n);
1792 vlib_set_trace_count (vm, node, n_trace - n);
1796 _vec_len (d_trace_save) = 0;
1797 _vec_len (d_trace_buffers) = 0;
1800 /* Don't keep a reference to b_last if we don't have to.
1801 Otherwise we can over-write a next_buffer pointer after already haven
1802 enqueued a packet. */
1805 b_last->next_buffer = ~0;
1809 dq->rx.n_descriptors_done_this_call = n_done;
1810 dq->rx.n_descriptors_done_total += n_done;
1811 dq->rx.is_start_of_packet = is_sop;
1812 dq->rx.saved_start_of_packet_buffer_index = bi_sop;
1813 dq->rx.saved_last_buffer_index = bi_last;
1814 dq->rx.saved_start_of_packet_next_index = next_index_sop;
1815 dq->rx.next_index = next_index;
1816 dq->rx.n_bytes += n_bytes;
1823 ixge_rx_queue (ixge_main_t * xm,
1825 vlib_node_runtime_t * node, u32 queue_index)
1827 ixge_dma_queue_t *dq =
1828 vec_elt_at_index (xd->dma_queues[VLIB_RX], queue_index);
1829 ixge_dma_regs_t *dr = get_dma_regs (xd, VLIB_RX, dq->queue_index);
1830 uword n_packets = 0;
1831 u32 hw_head_index, sw_head_index;
1833 /* One time initialization. */
1837 dq->rx.is_start_of_packet = 1;
1838 dq->rx.saved_start_of_packet_buffer_index = ~0;
1839 dq->rx.saved_last_buffer_index = ~0;
1842 dq->rx.next_index = node->cached_next_index;
1844 dq->rx.n_descriptors_done_total = 0;
1845 dq->rx.n_descriptors_done_this_call = 0;
1848 /* Fetch head from hardware and compare to where we think we are. */
1849 hw_head_index = dr->head_index;
1850 sw_head_index = dq->head_index;
1852 if (hw_head_index == sw_head_index)
1855 if (hw_head_index < sw_head_index)
1857 u32 n_tried = dq->n_descriptors - sw_head_index;
1858 n_packets += ixge_rx_queue_no_wrap (xm, xd, dq, sw_head_index, n_tried);
1860 ixge_ring_add (dq, sw_head_index,
1861 dq->rx.n_descriptors_done_this_call);
1863 if (dq->rx.n_descriptors_done_this_call != n_tried)
1866 if (hw_head_index >= sw_head_index)
1868 u32 n_tried = hw_head_index - sw_head_index;
1869 n_packets += ixge_rx_queue_no_wrap (xm, xd, dq, sw_head_index, n_tried);
1871 ixge_ring_add (dq, sw_head_index,
1872 dq->rx.n_descriptors_done_this_call);
1876 dq->head_index = sw_head_index;
1878 ixge_ring_add (dq, dq->tail_index, dq->rx.n_descriptors_done_total);
1880 /* Give tail back to hardware. */
1881 CLIB_MEMORY_BARRIER ();
1883 dr->tail_index = dq->tail_index;
1885 vlib_increment_combined_counter (vnet_main.
1886 interface_main.combined_sw_if_counters +
1887 VNET_INTERFACE_COUNTER_RX,
1889 xd->vlib_sw_if_index, n_packets,
1896 ixge_interrupt (ixge_main_t * xm, ixge_device_t * xd, u32 i)
1898 vlib_main_t *vm = xm->vlib_main;
1899 ixge_regs_t *r = xd->regs;
1903 ELOG_TYPE_DECLARE (e) =
1905 .function = (char *) __FUNCTION__,.format =
1906 "ixge %d, %s",.format_args = "i1t1",.n_enum_strings =
1913 "link status change",
1914 "linksec key exchange",
1915 "manageability event",
1921 "ecc", "descriptor handler error", "tcp timer", "other",},};
1927 ed = ELOG_DATA (&vm->elog_main, e);
1928 ed->instance = xd->device_index;
1933 u32 v = r->xge_mac.link_status;
1934 uword is_up = (v & (1 << 30)) != 0;
1936 ELOG_TYPE_DECLARE (e) =
1938 .function = (char *) __FUNCTION__,.format =
1939 "ixge %d, link status change 0x%x",.format_args = "i4i4",};
1942 u32 instance, link_status;
1944 ed = ELOG_DATA (&vm->elog_main, e);
1945 ed->instance = xd->device_index;
1946 ed->link_status = v;
1947 xd->link_status_at_last_link_change = v;
1949 vlib_process_signal_event (vm, ixge_process_node.index,
1951 ((is_up << 31) | xd->vlib_hw_if_index));
1956 clean_block (u32 * b, u32 * t, u32 n_left)
1962 u32 bi0, bi1, bi2, bi3;
1999 ixge_tx_queue (ixge_main_t * xm, ixge_device_t * xd, u32 queue_index)
2001 vlib_main_t *vm = xm->vlib_main;
2002 ixge_dma_queue_t *dq =
2003 vec_elt_at_index (xd->dma_queues[VLIB_TX], queue_index);
2004 u32 n_clean, *b, *t, *t0;
2005 i32 n_hw_owned_descriptors;
2006 i32 first_to_clean, last_to_clean;
2009 /* Handle case where head write back pointer update
2010 * arrives after the interrupt during high PCI bus loads.
2012 while ((dq->head_index == dq->tx.head_index_write_back[0]) &&
2013 dq->tx.n_buffers_on_ring && (dq->head_index != dq->tail_index))
2016 if (IXGE_HWBP_RACE_ELOG && (hwbp_race == 1))
2018 ELOG_TYPE_DECLARE (e) =
2020 .function = (char *) __FUNCTION__,.format =
2021 "ixge %d tx head index race: head %4d, tail %4d, buffs %4d",.format_args
2025 u32 instance, head_index, tail_index, n_buffers_on_ring;
2027 ed = ELOG_DATA (&vm->elog_main, e);
2028 ed->instance = xd->device_index;
2029 ed->head_index = dq->head_index;
2030 ed->tail_index = dq->tail_index;
2031 ed->n_buffers_on_ring = dq->tx.n_buffers_on_ring;
2035 dq->head_index = dq->tx.head_index_write_back[0];
2036 n_hw_owned_descriptors = ixge_ring_sub (dq, dq->head_index, dq->tail_index);
2037 ASSERT (dq->tx.n_buffers_on_ring >= n_hw_owned_descriptors);
2038 n_clean = dq->tx.n_buffers_on_ring - n_hw_owned_descriptors;
2040 if (IXGE_HWBP_RACE_ELOG && hwbp_race)
2042 ELOG_TYPE_DECLARE (e) =
2044 .function = (char *) __FUNCTION__,.format =
2045 "ixge %d tx head index race: head %4d, hw_owned %4d, n_clean %4d, retries %d",.format_args
2049 u32 instance, head_index, n_hw_owned_descriptors, n_clean, retries;
2051 ed = ELOG_DATA (&vm->elog_main, e);
2052 ed->instance = xd->device_index;
2053 ed->head_index = dq->head_index;
2054 ed->n_hw_owned_descriptors = n_hw_owned_descriptors;
2055 ed->n_clean = n_clean;
2056 ed->retries = hwbp_race;
2060 * This function used to wait until hardware owned zero descriptors.
2061 * At high PPS rates, that doesn't happen until the TX ring is
2062 * completely full of descriptors which need to be cleaned up.
2063 * That, in turn, causes TX ring-full drops and/or long RX service
2069 /* Clean the n_clean descriptors prior to the reported hardware head */
2070 last_to_clean = dq->head_index - 1;
2071 last_to_clean = (last_to_clean < 0) ? last_to_clean + dq->n_descriptors :
2074 first_to_clean = (last_to_clean) - (n_clean - 1);
2075 first_to_clean = (first_to_clean < 0) ? first_to_clean + dq->n_descriptors :
2078 vec_resize (xm->tx_buffers_pending_free, dq->n_descriptors - 1);
2079 t0 = t = xm->tx_buffers_pending_free;
2080 b = dq->descriptor_buffer_indices + first_to_clean;
2082 /* Wrap case: clean from first to end, then start to last */
2083 if (first_to_clean > last_to_clean)
2085 t += clean_block (b, t, (dq->n_descriptors - 1) - first_to_clean);
2087 b = dq->descriptor_buffer_indices;
2090 /* Typical case: clean from first to last */
2091 if (first_to_clean <= last_to_clean)
2092 t += clean_block (b, t, (last_to_clean - first_to_clean) + 1);
2097 vlib_buffer_free_no_next (vm, t0, n);
2098 ASSERT (dq->tx.n_buffers_on_ring >= n);
2099 dq->tx.n_buffers_on_ring -= n;
2100 _vec_len (xm->tx_buffers_pending_free) = 0;
2104 /* RX queue interrupts 0 thru 7; TX 8 thru 15. */
2106 ixge_interrupt_is_rx_queue (uword i)
2112 ixge_interrupt_is_tx_queue (uword i)
2114 return i >= 8 && i < 16;
2118 ixge_tx_queue_to_interrupt (uword i)
2124 ixge_rx_queue_to_interrupt (uword i)
2130 ixge_interrupt_rx_queue (uword i)
2132 ASSERT (ixge_interrupt_is_rx_queue (i));
2137 ixge_interrupt_tx_queue (uword i)
2139 ASSERT (ixge_interrupt_is_tx_queue (i));
2144 ixge_device_input (ixge_main_t * xm,
2145 ixge_device_t * xd, vlib_node_runtime_t * node)
2147 ixge_regs_t *r = xd->regs;
2149 uword n_rx_packets = 0;
2151 s = r->interrupt.status_write_1_to_set;
2153 r->interrupt.status_write_1_to_clear = s;
2156 foreach_set_bit (i, s, ({
2157 if (ixge_interrupt_is_rx_queue (i))
2158 n_rx_packets += ixge_rx_queue (xm, xd, node, ixge_interrupt_rx_queue (i));
2160 else if (ixge_interrupt_is_tx_queue (i))
2161 ixge_tx_queue (xm, xd, ixge_interrupt_tx_queue (i));
2164 ixge_interrupt (xm, xd, i);
2168 return n_rx_packets;
2172 ixge_input (vlib_main_t * vm, vlib_node_runtime_t * node, vlib_frame_t * f)
2174 ixge_main_t *xm = &ixge_main;
2176 uword n_rx_packets = 0;
2178 if (node->state == VLIB_NODE_STATE_INTERRUPT)
2182 /* Loop over devices with interrupts. */
2184 foreach_set_bit (i, node->runtime_data[0], ({
2185 xd = vec_elt_at_index (xm->devices, i);
2186 n_rx_packets += ixge_device_input (xm, xd, node);
2188 /* Re-enable interrupts since we're going to stay in interrupt mode. */
2189 if (! (node->flags & VLIB_NODE_FLAG_SWITCH_FROM_INTERRUPT_TO_POLLING_MODE))
2190 xd->regs->interrupt.enable_write_1_to_set = ~0;
2194 /* Clear mask of devices with pending interrupts. */
2195 node->runtime_data[0] = 0;
2199 /* Poll all devices for input/interrupts. */
2200 vec_foreach (xd, xm->devices)
2202 n_rx_packets += ixge_device_input (xm, xd, node);
2204 /* Re-enable interrupts when switching out of polling mode. */
2206 VLIB_NODE_FLAG_SWITCH_FROM_POLLING_TO_INTERRUPT_MODE)
2207 xd->regs->interrupt.enable_write_1_to_set = ~0;
2211 return n_rx_packets;
2214 static char *ixge_error_strings[] = {
2221 VLIB_REGISTER_NODE (ixge_input_node, static) = {
2222 .function = ixge_input,
2223 .type = VLIB_NODE_TYPE_INPUT,
2224 .name = "ixge-input",
2226 /* Will be enabled if/when hardware is detected. */
2227 .state = VLIB_NODE_STATE_DISABLED,
2229 .format_buffer = format_ethernet_header_with_length,
2230 .format_trace = format_ixge_rx_dma_trace,
2232 .n_errors = IXGE_N_ERROR,
2233 .error_strings = ixge_error_strings,
2235 .n_next_nodes = IXGE_RX_N_NEXT,
2237 [IXGE_RX_NEXT_DROP] = "error-drop",
2238 [IXGE_RX_NEXT_ETHERNET_INPUT] = "ethernet-input",
2239 [IXGE_RX_NEXT_IP4_INPUT] = "ip4-input",
2240 [IXGE_RX_NEXT_IP6_INPUT] = "ip6-input",
2244 VLIB_NODE_FUNCTION_MULTIARCH_CLONE (ixge_input)
2245 CLIB_MULTIARCH_SELECT_FN (ixge_input)
2249 format_ixge_device_name (u8 * s, va_list * args)
2251 u32 i = va_arg (*args, u32);
2252 ixge_main_t *xm = &ixge_main;
2253 ixge_device_t *xd = vec_elt_at_index (xm->devices, i);
2254 return format (s, "TenGigabitEthernet%U",
2255 format_vlib_pci_handle, &xd->pci_device.bus_address);
2258 #define IXGE_COUNTER_IS_64_BIT (1 << 0)
2259 #define IXGE_COUNTER_NOT_CLEAR_ON_READ (1 << 1)
2261 static u8 ixge_counter_flags[] = {
2263 #define _64(a,f) IXGE_COUNTER_IS_64_BIT,
2264 foreach_ixge_counter
2270 ixge_update_counters (ixge_device_t * xd)
2272 /* Byte offset for counter registers. */
2273 static u32 reg_offsets[] = {
2274 #define _(a,f) (a) / sizeof (u32),
2275 #define _64(a,f) _(a,f)
2276 foreach_ixge_counter
2280 volatile u32 *r = (volatile u32 *) xd->regs;
2283 for (i = 0; i < ARRAY_LEN (xd->counters); i++)
2285 u32 o = reg_offsets[i];
2286 xd->counters[i] += r[o];
2287 if (ixge_counter_flags[i] & IXGE_COUNTER_NOT_CLEAR_ON_READ)
2289 if (ixge_counter_flags[i] & IXGE_COUNTER_IS_64_BIT)
2290 xd->counters[i] += (u64) r[o + 1] << (u64) 32;
2295 format_ixge_device_id (u8 * s, va_list * args)
2297 u32 device_id = va_arg (*args, u32);
2301 #define _(f,n) case n: t = #f; break;
2302 foreach_ixge_pci_device_id;
2309 s = format (s, "unknown 0x%x", device_id);
2311 s = format (s, "%s", t);
2316 format_ixge_link_status (u8 * s, va_list * args)
2318 ixge_device_t *xd = va_arg (*args, ixge_device_t *);
2319 u32 v = xd->link_status_at_last_link_change;
2321 s = format (s, "%s", (v & (1 << 30)) ? "up" : "down");
2325 "1g", "10g parallel", "10g serial", "autoneg",
2328 "unknown", "100m", "1g", "10g",
2330 s = format (s, ", mode %s, speed %s",
2331 modes[(v >> 26) & 3], speeds[(v >> 28) & 3]);
2338 format_ixge_device (u8 * s, va_list * args)
2340 u32 dev_instance = va_arg (*args, u32);
2341 CLIB_UNUSED (int verbose) = va_arg (*args, int);
2342 ixge_main_t *xm = &ixge_main;
2343 ixge_device_t *xd = vec_elt_at_index (xm->devices, dev_instance);
2344 ixge_phy_t *phy = xd->phys + xd->phy_index;
2345 uword indent = format_get_indent (s);
2347 ixge_update_counters (xd);
2348 xd->link_status_at_last_link_change = xd->regs->xge_mac.link_status;
2350 s = format (s, "Intel 8259X: id %U\n%Ulink %U",
2351 format_ixge_device_id, xd->device_id,
2352 format_white_space, indent + 2, format_ixge_link_status, xd);
2356 s = format (s, "\n%UPCIe %U", format_white_space, indent + 2,
2357 format_vlib_pci_link_speed, &xd->pci_device);
2360 s = format (s, "\n%U", format_white_space, indent + 2);
2361 if (phy->mdio_address != ~0)
2362 s = format (s, "PHY address %d, id 0x%x", phy->mdio_address, phy->id);
2363 else if (xd->sfp_eeprom.id == SFP_ID_sfp)
2364 s = format (s, "SFP %U", format_sfp_eeprom, &xd->sfp_eeprom);
2366 s = format (s, "PHY not found");
2370 ixge_dma_queue_t *dq = vec_elt_at_index (xd->dma_queues[VLIB_RX], 0);
2371 ixge_dma_regs_t *dr = get_dma_regs (xd, VLIB_RX, 0);
2372 u32 hw_head_index = dr->head_index;
2373 u32 sw_head_index = dq->head_index;
2376 nitems = ixge_ring_sub (dq, hw_head_index, sw_head_index);
2377 s = format (s, "\n%U%d unprocessed, %d total buffers on rx queue 0 ring",
2378 format_white_space, indent + 2, nitems, dq->n_descriptors);
2380 s = format (s, "\n%U%d buffers in driver rx cache",
2381 format_white_space, indent + 2,
2382 vec_len (xm->rx_buffers_to_add));
2384 s = format (s, "\n%U%d buffers on tx queue 0 ring",
2385 format_white_space, indent + 2,
2386 xd->dma_queues[VLIB_TX][0].tx.n_buffers_on_ring);
2391 static char *names[] = {
2393 #define _64(a,f) _(a,f)
2394 foreach_ixge_counter
2399 for (i = 0; i < ARRAY_LEN (names); i++)
2401 v = xd->counters[i] - xd->counters_last_clear[i];
2403 s = format (s, "\n%U%-40U%16Ld",
2404 format_white_space, indent + 2,
2405 format_c_identifier, names[i], v);
2413 ixge_clear_hw_interface_counters (u32 instance)
2415 ixge_main_t *xm = &ixge_main;
2416 ixge_device_t *xd = vec_elt_at_index (xm->devices, instance);
2417 ixge_update_counters (xd);
2418 memcpy (xd->counters_last_clear, xd->counters, sizeof (xd->counters));
2422 * Dynamically redirect all pkts from a specific interface
2423 * to the specified node
2426 ixge_set_interface_next_node (vnet_main_t * vnm, u32 hw_if_index,
2429 ixge_main_t *xm = &ixge_main;
2430 vnet_hw_interface_t *hw = vnet_get_hw_interface (vnm, hw_if_index);
2431 ixge_device_t *xd = vec_elt_at_index (xm->devices, hw->dev_instance);
2433 /* Shut off redirection */
2434 if (node_index == ~0)
2436 xd->per_interface_next_index = node_index;
2440 xd->per_interface_next_index =
2441 vlib_node_add_next (xm->vlib_main, ixge_input_node.index, node_index);
2446 VNET_DEVICE_CLASS (ixge_device_class) = {
2448 .tx_function = ixge_interface_tx,
2449 .format_device_name = format_ixge_device_name,
2450 .format_device = format_ixge_device,
2451 .format_tx_trace = format_ixge_tx_dma_trace,
2452 .clear_counters = ixge_clear_hw_interface_counters,
2453 .admin_up_down_function = ixge_interface_admin_up_down,
2454 .rx_redirect_to_node = ixge_set_interface_next_node,
2458 #define IXGE_N_BYTES_IN_RX_BUFFER (2048) // DAW-HACK: Set Rx buffer size so all packets < ETH_MTU_SIZE fit in the buffer (i.e. sop & eop for all descriptors).
2460 static clib_error_t *
2461 ixge_dma_init (ixge_device_t * xd, vlib_rx_or_tx_t rt, u32 queue_index)
2463 ixge_main_t *xm = &ixge_main;
2464 vlib_main_t *vm = xm->vlib_main;
2465 ixge_dma_queue_t *dq;
2466 clib_error_t *error = 0;
2468 vec_validate (xd->dma_queues[rt], queue_index);
2469 dq = vec_elt_at_index (xd->dma_queues[rt], queue_index);
2471 if (!xm->n_descriptors_per_cache_line)
2472 xm->n_descriptors_per_cache_line =
2473 CLIB_CACHE_LINE_BYTES / sizeof (dq->descriptors[0]);
2475 if (!xm->n_bytes_in_rx_buffer)
2476 xm->n_bytes_in_rx_buffer = IXGE_N_BYTES_IN_RX_BUFFER;
2477 xm->n_bytes_in_rx_buffer = round_pow2 (xm->n_bytes_in_rx_buffer, 1024);
2478 if (!xm->vlib_buffer_free_list_index)
2480 xm->vlib_buffer_free_list_index =
2481 vlib_buffer_get_or_create_free_list (vm, xm->n_bytes_in_rx_buffer,
2483 ASSERT (xm->vlib_buffer_free_list_index != 0);
2486 if (!xm->n_descriptors[rt])
2487 xm->n_descriptors[rt] = 4 * VLIB_FRAME_SIZE;
2489 dq->queue_index = queue_index;
2491 round_pow2 (xm->n_descriptors[rt], xm->n_descriptors_per_cache_line);
2492 dq->head_index = dq->tail_index = 0;
2494 dq->descriptors = vlib_physmem_alloc_aligned (vm, &error,
2496 sizeof (dq->descriptors[0]),
2497 128 /* per chip spec */ );
2501 memset (dq->descriptors, 0,
2502 dq->n_descriptors * sizeof (dq->descriptors[0]));
2503 vec_resize (dq->descriptor_buffer_indices, dq->n_descriptors);
2509 n_alloc = vlib_buffer_alloc_from_free_list
2510 (vm, dq->descriptor_buffer_indices,
2511 vec_len (dq->descriptor_buffer_indices),
2512 xm->vlib_buffer_free_list_index);
2513 ASSERT (n_alloc == vec_len (dq->descriptor_buffer_indices));
2514 for (i = 0; i < n_alloc; i++)
2517 vlib_get_buffer (vm, dq->descriptor_buffer_indices[i]);
2518 dq->descriptors[i].rx_to_hw.tail_address =
2519 vlib_physmem_virtual_to_physical (vm, b->data);
2526 dq->tx.head_index_write_back =
2527 vlib_physmem_alloc (vm, &error, CLIB_CACHE_LINE_BYTES);
2529 for (i = 0; i < dq->n_descriptors; i++)
2530 dq->descriptors[i].tx = xm->tx_descriptor_template;
2532 vec_validate (xm->tx_buffers_pending_free, dq->n_descriptors - 1);
2536 ixge_dma_regs_t *dr = get_dma_regs (xd, rt, queue_index);
2539 a = vlib_physmem_virtual_to_physical (vm, dq->descriptors);
2540 dr->descriptor_address[0] = a & 0xFFFFFFFF;
2541 dr->descriptor_address[1] = a >> (u64) 32;
2542 dr->n_descriptor_bytes = dq->n_descriptors * sizeof (dq->descriptors[0]);
2543 dq->head_index = dq->tail_index = 0;
2547 ASSERT ((xm->n_bytes_in_rx_buffer / 1024) < 32);
2548 dr->rx_split_control =
2549 ( /* buffer size */ ((xm->n_bytes_in_rx_buffer / 1024) << 0)
2550 | ( /* lo free descriptor threshold (units of 64 descriptors) */
2551 (1 << 22)) | ( /* descriptor type: advanced one buffer */
2552 (1 << 25)) | ( /* drop if no descriptors available */
2555 /* Give hardware all but last 16 cache lines' worth of descriptors. */
2556 dq->tail_index = dq->n_descriptors -
2557 16 * xm->n_descriptors_per_cache_line;
2561 /* Make sure its initialized before hardware can get to it. */
2562 dq->tx.head_index_write_back[0] = dq->head_index;
2565 vlib_physmem_virtual_to_physical (vm, dq->tx.head_index_write_back);
2566 dr->tx.head_index_write_back_address[0] = /* enable bit */ 1 | a;
2567 dr->tx.head_index_write_back_address[1] = (u64) a >> (u64) 32;
2570 /* DMA on 82599 does not work with [13] rx data write relaxed ordering
2571 and [12] undocumented set. */
2573 dr->dca_control &= ~((1 << 13) | (1 << 12));
2575 CLIB_MEMORY_BARRIER ();
2579 xd->regs->tx_dma_control |= (1 << 0);
2580 dr->control |= ((32 << 0) /* prefetch threshold */
2581 | (64 << 8) /* host threshold */
2582 | (0 << 16) /* writeback threshold */ );
2585 /* Enable this queue and wait for hardware to initialize
2586 before adding to tail. */
2589 dr->control |= 1 << 25;
2590 while (!(dr->control & (1 << 25)))
2594 /* Set head/tail indices and enable DMA. */
2595 dr->head_index = dq->head_index;
2596 dr->tail_index = dq->tail_index;
2603 ixge_flag_change (vnet_main_t * vnm, vnet_hw_interface_t * hw, u32 flags)
2608 ixge_main_t *xm = &ixge_main;
2610 xd = vec_elt_at_index (xm->devices, hw->dev_instance);
2613 old = r->filter_control;
2615 if (flags & ETHERNET_INTERFACE_FLAG_ACCEPT_ALL)
2616 r->filter_control = old | (1 << 9) /* unicast promiscuous */ ;
2618 r->filter_control = old & ~(1 << 9);
2624 ixge_device_init (ixge_main_t * xm)
2626 vnet_main_t *vnm = vnet_get_main ();
2629 /* Reset chip(s). */
2630 vec_foreach (xd, xm->devices)
2632 ixge_regs_t *r = xd->regs;
2633 const u32 reset_bit = (1 << 26) | (1 << 3);
2635 r->control |= reset_bit;
2637 /* No need to suspend. Timed to take ~1e-6 secs */
2638 while (r->control & reset_bit)
2641 /* Software loaded. */
2642 r->extended_control |= (1 << 28);
2646 /* Register ethernet interface. */
2650 clib_error_t *error;
2652 addr32[0] = r->rx_ethernet_address0[0][0];
2653 addr32[1] = r->rx_ethernet_address0[0][1];
2654 for (i = 0; i < 6; i++)
2655 addr8[i] = addr32[i / 4] >> ((i % 4) * 8);
2657 error = ethernet_register_interface
2658 (vnm, ixge_device_class.index, xd->device_index,
2659 /* ethernet address */ addr8,
2660 &xd->vlib_hw_if_index, ixge_flag_change);
2662 clib_error_report (error);
2666 vnet_sw_interface_t *sw =
2667 vnet_get_hw_sw_interface (vnm, xd->vlib_hw_if_index);
2668 xd->vlib_sw_if_index = sw->sw_if_index;
2671 ixge_dma_init (xd, VLIB_RX, /* queue_index */ 0);
2673 xm->n_descriptors[VLIB_TX] = 20 * VLIB_FRAME_SIZE;
2675 ixge_dma_init (xd, VLIB_TX, /* queue_index */ 0);
2677 /* RX/TX queue 0 gets mapped to interrupt bits 0 & 8. */
2678 r->interrupt.queue_mapping[0] = (( /* valid bit */ (1 << 7) |
2679 ixge_rx_queue_to_interrupt (0)) << 0);
2681 r->interrupt.queue_mapping[0] |= (( /* valid bit */ (1 << 7) |
2682 ixge_tx_queue_to_interrupt (0)) << 8);
2684 /* No use in getting too many interrupts.
2685 Limit them to one every 3/4 ring size at line rate
2687 No need for this since kernel/vlib main loop provides adequate interrupt
2691 f64 line_rate_max_pps =
2692 10e9 / (8 * (64 + /* interframe padding */ 20));
2693 ixge_throttle_queue_interrupt (r, 0,
2694 .75 * xm->n_descriptors[VLIB_RX] /
2698 /* Accept all multicast and broadcast packets. Should really add them
2699 to the dst_ethernet_address register array. */
2700 r->filter_control |= (1 << 10) | (1 << 8);
2702 /* Enable frames up to size in mac frame size register. */
2703 r->xge_mac.control |= 1 << 2;
2704 r->xge_mac.rx_max_frame_size = (9216 + 14) << 16;
2706 /* Enable all interrupts. */
2707 if (!IXGE_ALWAYS_POLL)
2708 r->interrupt.enable_write_1_to_set = ~0;
2713 ixge_process (vlib_main_t * vm, vlib_node_runtime_t * rt, vlib_frame_t * f)
2715 vnet_main_t *vnm = vnet_get_main ();
2716 ixge_main_t *xm = &ixge_main;
2718 uword event_type, *event_data = 0;
2719 f64 timeout, link_debounce_deadline;
2721 ixge_device_init (xm);
2723 /* Clear all counters. */
2724 vec_foreach (xd, xm->devices)
2726 ixge_update_counters (xd);
2727 memset (xd->counters, 0, sizeof (xd->counters));
2731 link_debounce_deadline = 1e70;
2735 /* 36 bit stat counters could overflow in ~50 secs.
2736 We poll every 30 secs to be conservative. */
2737 vlib_process_wait_for_event_or_clock (vm, timeout);
2739 event_type = vlib_process_get_events (vm, &event_data);
2743 case EVENT_SET_FLAGS:
2745 link_debounce_deadline = vlib_time_now (vm) + 1e-3;
2750 /* No events found: timer expired. */
2751 if (vlib_time_now (vm) > link_debounce_deadline)
2753 vec_foreach (xd, xm->devices)
2755 ixge_regs_t *r = xd->regs;
2756 u32 v = r->xge_mac.link_status;
2757 uword is_up = (v & (1 << 30)) != 0;
2759 vnet_hw_interface_set_flags
2760 (vnm, xd->vlib_hw_if_index,
2761 is_up ? VNET_HW_INTERFACE_FLAG_LINK_UP : 0);
2763 link_debounce_deadline = 1e70;
2773 _vec_len (event_data) = 0;
2775 /* Query stats every 30 secs. */
2777 f64 now = vlib_time_now (vm);
2778 if (now - xm->time_last_stats_update > 30)
2780 xm->time_last_stats_update = now;
2781 vec_foreach (xd, xm->devices) ixge_update_counters (xd);
2789 static vlib_node_registration_t ixge_process_node = {
2790 .function = ixge_process,
2791 .type = VLIB_NODE_TYPE_PROCESS,
2792 .name = "ixge-process",
2796 ixge_init (vlib_main_t * vm)
2798 ixge_main_t *xm = &ixge_main;
2799 clib_error_t *error;
2802 memset (&xm->tx_descriptor_template, 0,
2803 sizeof (xm->tx_descriptor_template));
2804 memset (&xm->tx_descriptor_template_mask, 0,
2805 sizeof (xm->tx_descriptor_template_mask));
2806 xm->tx_descriptor_template.status0 =
2807 (IXGE_TX_DESCRIPTOR_STATUS0_ADVANCED |
2808 IXGE_TX_DESCRIPTOR_STATUS0_IS_ADVANCED |
2809 IXGE_TX_DESCRIPTOR_STATUS0_INSERT_FCS);
2810 xm->tx_descriptor_template_mask.status0 = 0xffff;
2811 xm->tx_descriptor_template_mask.status1 = 0x00003fff;
2813 xm->tx_descriptor_template_mask.status0 &=
2814 ~(IXGE_TX_DESCRIPTOR_STATUS0_IS_END_OF_PACKET
2815 | IXGE_TX_DESCRIPTOR_STATUS0_REPORT_STATUS);
2816 xm->tx_descriptor_template_mask.status1 &=
2817 ~(IXGE_TX_DESCRIPTOR_STATUS1_DONE);
2819 error = vlib_call_init_function (vm, pci_bus_init);
2824 VLIB_INIT_FUNCTION (ixge_init);
2828 ixge_pci_intr_handler (vlib_pci_device_t * dev)
2830 ixge_main_t *xm = &ixge_main;
2831 vlib_main_t *vm = xm->vlib_main;
2833 vlib_node_set_interrupt_pending (vm, ixge_input_node.index);
2835 /* Let node know which device is interrupting. */
2837 vlib_node_runtime_t *rt =
2838 vlib_node_get_runtime (vm, ixge_input_node.index);
2839 rt->runtime_data[0] |= 1 << dev->private_data;
2843 static clib_error_t *
2844 ixge_pci_init (vlib_main_t * vm, vlib_pci_device_t * dev)
2846 ixge_main_t *xm = &ixge_main;
2847 clib_error_t *error;
2851 /* Device found: make sure we have dma memory. */
2852 if (unix_physmem_is_fake (vm))
2853 return clib_error_return (0, "no physical memory available");
2855 error = vlib_pci_map_resource (dev, 0, &r);
2859 vec_add2 (xm->devices, xd, 1);
2861 if (vec_len (xm->devices) == 1)
2863 ixge_input_node.function = ixge_input_multiarch_select ();
2866 xd->pci_device = dev[0];
2867 xd->device_id = xd->pci_device.config0.header.device_id;
2869 xd->device_index = xd - xm->devices;
2870 xd->pci_function = dev->bus_address.function;
2871 xd->per_interface_next_index = ~0;
2874 /* Chip found so enable node. */
2876 vlib_node_set_state (vm, ixge_input_node.index,
2878 ? VLIB_NODE_STATE_POLLING
2879 : VLIB_NODE_STATE_INTERRUPT));
2881 dev->private_data = xd->device_index;
2884 if (vec_len (xm->devices) == 1)
2886 vlib_register_node (vm, &ixge_process_node);
2887 xm->process_node_index = ixge_process_node.index;
2890 error = vlib_pci_bus_master_enable (dev);
2895 return vlib_pci_intr_enable (dev);
2899 PCI_REGISTER_DEVICE (ixge_pci_device_registration,static) = {
2900 .init_function = ixge_pci_init,
2901 .interrupt_handler = ixge_pci_intr_handler,
2902 .supported_devices = {
2903 #define _(t,i) { .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = i, },
2904 foreach_ixge_pci_device_id
2912 ixge_set_next_node (ixge_rx_next_t next, char *name)
2914 vlib_node_registration_t *r = &ixge_input_node;
2918 case IXGE_RX_NEXT_IP4_INPUT:
2919 case IXGE_RX_NEXT_IP6_INPUT:
2920 case IXGE_RX_NEXT_ETHERNET_INPUT:
2921 r->next_nodes[next] = name;
2925 clib_warning ("%s: illegal next %d\n", __FUNCTION__, next);
2932 * fd.io coding-style-patch-verification: ON
2935 * eval: (c-set-style "gnu")