/* SPDX-License-Identifier: BSD-3-Clause * * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. * Copyright 2017 NXP * */ #ifndef __DPDK_RXTX_H__ #define __DPDK_RXTX_H__ /* internal offset from where IC is copied to packet buffer*/ #define DEFAULT_ICIOF 32 /* IC transfer size */ #define DEFAULT_ICSZ 48 /* IC offsets from buffer header address */ #define DEFAULT_RX_ICEOF 16 #define DEFAULT_TX_ICEOF 16 /* * Values for the L3R field of the FM Parse Results */ /* L3 Type field: First IP Present IPv4 */ #define DPAA_L3_PARSE_RESULT_IPV4 0x80 /* L3 Type field: First IP Present IPv6 */ #define DPAA_L3_PARSE_RESULT_IPV6 0x40 /* Values for the L4R field of the FM Parse Results * See $8.8.4.7.20 - L4 HXS - L4 Results from DPAA-Rev2 Reference Manual. */ /* L4 Type field: UDP */ #define DPAA_L4_PARSE_RESULT_UDP 0x40 /* L4 Type field: TCP */ #define DPAA_L4_PARSE_RESULT_TCP 0x20 #define DPAA_MAX_DEQUEUE_NUM_FRAMES 63 /**