- direction, hence two sets of latency values are reported per test
- case.
-- Reported latency values are aggregate across tested topology.
-- +/- 1 usec is the measurement accuracy advertised by TRex TG for the
- setup used.
-- TG setup introduces an always-on Tx/Rx interface latency of about 2
- * 2 usec per direction induced by TRex SW writing and reading packet
- timestamps on CPU cores.
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+ direction, hence two sets of latency values are reported per test case
+ (marked as E-W and W-E).
+- +/- 1 usec is the measurement accuracy of TRex TG and the data in HDRH
+ latency values distribution is rounded to microseconds.
+- TRex TG introduces a (background) always-on Tx + Rx latency bias of 4
+ usec on average per direction resulting from TRex software writing and
+ reading packet timestamps on CPU cores. Quoted values are based on TG
+ back-to-back latency measurements.
+- Latency graphs are not smoothed, each latency value has its own
+ horizontal line across corresponding packet percentiles.
+- Percentiles are shown on X-axis using a logarithmic scale, so the
+ maximal latency value (ending at 100% percentile) would be in
+ infinity. The graphs are cut at 99.9999% (hover information still
+ lists 100%).
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