+
+.. _physical_testbeds_3n_dnv:
+
+3-Node Atom Denverton (3n-dnv)
+------------------------------
+
+One 3n-dnv testbed is built with: i) one SuperMicro SYS-7049GP-TRT
+server acting as TG and equipped with two Intel Xeon Skylake Platinum
+8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one
+SuperMicro SYS-E300-9A server acting as SUT and equipped with one Intel
+Atom C3858 processor (12 MB Cache, 2.00 GHz, 12 cores). 3n-dnv physical
+topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-3n-dnv}
+ \label{fig:testbed-3n-dnv}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-3n-dnv.svg
+ :alt: testbed-3n-dnv
+ :align: center
+
+SUT1 and SUT2 NICs:
+
+#. NIC-1: x553 2p10GE fiber Intel.
+#. NIC-2: x553 2p10GE copper Intel.
+
+TG NICs:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+
+.. _physical_testbeds_3n_alt:
+
+3-Node ARM Altra (3n-alt)
+---------------------------
+
+One 3n-tsh testbed is built with: i) one SuperMicro SYS-740GP-TNRT
+server acting as TG and equipped with two Intel Xeon Icelake Platinum
+8358 processors (80 MB Cache, 2.60 GHz, 32 cores), and ii) one Ampere
+Altra server acting as SUT and equipped with two Q80-30 processors
+(80* ARM Neoverse N1). 3n-alt physical topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-3n-alt}
+ \label{fig:testbed-3n-alt}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-3n-alt.svg
+ :alt: testbed-3n-alt
+ :align: center
+
+SUT1 and SUT2 NICs:
+
+#. NIC-1: xl710-QDA2-2p40GE Intel.
+
+TG NICs:
+
+#. NIC-1: xxv710-DA2-2p25GE Intel.
+#. NIC-2: xl710-QDA2-2p40GE Intel.
+#. NIC-3: e810-XXVDA4-4p25GE Intel.
+#. NIC-4: e810-2CQDA2-2p100GE Intel.
+
+.. _physical_testbeds_3n_tsh:
+
+3-Node ARM TaiShan (3n-tsh)
+---------------------------
+
+One 3n-tsh testbed is built with: i) one SuperMicro SYS-7049GP-TRT
+server acting as TG and equipped with two Intel Xeon Skylake Platinum
+8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one Huawei
+TaiShan 2280 server acting as SUT and equipped with one hip07-d05
+processor (64* ARM Cortex-A72). 3n-tsh physical topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-3n-tsh}
+ \label{fig:testbed-3n-tsh}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-3n-tsh.svg
+ :alt: testbed-3n-tsh
+ :align: center
+
+SUT1 and SUT2 NICs:
+
+#. NIC-1: connectx4 2p25GE Mellanox.
+#. NIC-2: x520 2p10GE Intel.
+
+TG NICs:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: xl710-QDA2 2p40GE Intel.
+
+.. _physical_testbeds_2n_tx2:
+
+2-Node ARM ThunderX2 (2n-tx2)
+-----------------------------
+
+One 2n-tx2 testbed is built with: i) one SuperMicro SYS-7049GP-TRT
+server acting as TG and equipped with two Intel Xeon Skylake Platinum
+8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one Marvell
+ThnderX2 9975 (28* ThunderX2) server acting as SUT and equipped with two
+ThunderX2 ARMv8 CN9975 processors. 2n-tx2 physical topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-2n-tx2}
+ \label{fig:testbed-2n-tx2}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-2n-tx2.svg
+ :alt: testbed-2n-tx2
+ :align: center
+
+SUT NICs:
+
+#. NIC-1: xl710-QDA2 2p40GE Intel (not connected).
+#. NIC-2: xl710-QDA2 2p40GE Intel.
+
+TG NICs:
+
+#. NIC-1: xl710-QDA2 2p40GE Intel.
+
+.. _physical_testbeds_3n_snr:
+
+3-Node Atom Snowridge (3n-snr)
+------------------------------
+
+One 3n-snr testbed is built with: i) one SuperMicro SYS-740GP-TNRT
+server acting as TG and equipped with two Intel Xeon Icelake Platinum
+8358 processors (48 MB Cache, 2.60 GHz, 32 cores), and ii) SUT equipped with
+one Intel Atom P5362 processor (27 MB Cache, 2.20 GHz, 24 cores). 3n-snr
+physical topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-3n-snr}
+ \label{fig:testbed-3n-snr}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-3n-snr.svg
+ :alt: testbed-3n-snr
+ :align: center
+
+SUT1 and SUT2 NICs:
+
+#. NIC-1: e822cq-DA4 4p25GE fiber Intel.
+
+TG NICs:
+
+#. NIC-1: e810xxv-DA4 4p25GE Intel.