server as TG both connected in ring topology.
Tested SUT servers are based on a range of processors including Intel
server as TG both connected in ring topology.
Tested SUT servers are based on a range of processors including Intel
-Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascadelake-SP, Arm, Intel
+Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, Intel
Atom. More detailed description is provided in
:ref:`tested_physical_topologies`. Tested logical topologies are
described in :ref:`tested_logical_topologies`.
Atom. More detailed description is provided in
:ref:`tested_physical_topologies`. Tested logical topologies are
described in :ref:`tested_logical_topologies`.
Complete technical specifications of compute servers used in CSIT
physical testbeds are maintained in FD.io CSIT repository:
Complete technical specifications of compute servers used in CSIT
physical testbeds are maintained in FD.io CSIT repository:
`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and
`FD.io CSIT Testbeds - Xeon Haswell`_.
`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and
`FD.io CSIT Testbeds - Xeon Haswell`_.
Linux in clock cycles and how often interrupts happen. Using
`CPU core jitter tool <https://git.fd.io/pma_tools/tree/jitter>`_.
Linux in clock cycles and how often interrupts happen. Using
`CPU core jitter tool <https://git.fd.io/pma_tools/tree/jitter>`_.
system instances. Generally they come useful as a background data for
comparing data plane performance results across disparate servers.
system instances. Generally they come useful as a background data for
comparing data plane performance results across disparate servers.