Report: Configure rls2009.48

[csit.git] / docs / report / introduction / test_environment_sut_calib_tsh.rst

diff --git a/docs/report/introduction/test_environment_sut_calib_tsh.rst b/docs/report/introduction/test_environment_sut_calib_tsh.rst
index 139d30f..a503a42 100644 (file)
--- a/docs/report/introduction/test_environment_sut_calib_tsh.rst
+++ b/docs/report/introduction/test_environment_sut_calib_tsh.rst
@@ -1,5 +1,5 @@
-Calibration Data - TaiShan
---------------------------
+TaiShan
+~~~~~~~

 
 Following sections include sample calibration data measured on
 s17-t33-sut1 server running in one of the Cortex-A72 testbeds.
 
 Following sections include sample calibration data measured on
 s17-t33-sut1 server running in one of the Cortex-A72 testbeds.


@@ -9,7 +9,7 @@ same or similar values.
 
 
 Linux cmdline
 
 
 Linux cmdline

-~~~~~~~~~~~~~
+^^^^^^^^^^^^^

 
 ::
 
 
 ::
 


@@ -17,7 +17,7 @@ Linux cmdline
     BOOT_IMAGE=/boot/vmlinuz-4.15.0-54-generic root=/dev/mapper/huawei--1--vg-root ro isolcpus=1-15,17-31,33-47,49-63 nohz_full=1-15     17-31,33-47,49-63 rcu_nocbs=1-15     17-31,33-47,49-63 intel_iommu=on nmi_watchdog=0 audit=0 nosoftlockup processor.max_cstate=1 console=ttyAMA0,115200n8
 
 Linux uname
     BOOT_IMAGE=/boot/vmlinuz-4.15.0-54-generic root=/dev/mapper/huawei--1--vg-root ro isolcpus=1-15,17-31,33-47,49-63 nohz_full=1-15     17-31,33-47,49-63 rcu_nocbs=1-15     17-31,33-47,49-63 intel_iommu=on nmi_watchdog=0 audit=0 nosoftlockup processor.max_cstate=1 console=ttyAMA0,115200n8
 
 Linux uname

-~~~~~~~~~~~
+^^^^^^^^^^^

 
 ::
 
 
 ::
 


@@ -26,7 +26,7 @@ Linux uname
 
 
 System-level Core Jitter
 
 
 System-level Core Jitter

-~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^

 
 ::
 
 
 ::
 


@@ -78,3 +78,5 @@ System-level Core Jitter
         160022     169610       9588     160044     160022     173162    2580611072 3204390608         28
         160022     169254       9232     160044     160022     173162    1492189184 3204399760         29
         160022     169386       9364     160046     160022     173162     403767296 3204417762         30
         160022     169610       9588     160044     160022     173162    2580611072 3204390608         28
         160022     169254       9232     160044     160022     173162    1492189184 3204399760         29
         160022     169386       9364     160046     160022     173162     403767296 3204417762         30

+
+.. include:: ../introduction/test_environment_sut_meltspec_tsh.rst