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Report: Add VPP 2n-clx cx556a
[csit.git]
/
docs
/
report
/
vpp_performance_tests
/
packet_latency_graphs
/
container_memif.rst
diff --git
a/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
b/docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
index
0ffeef5
..
57bed13
100644
(file)
--- a/
docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
+++ b/
docs/report/vpp_performance_tests/packet_latency_graphs/container_memif.rst
@@
-13,15
+13,12
@@
VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls
19
01>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls
20
01>`_.
.. toctree::
.. toctree::
- container_memif-3n-hsw-x520
- container_memif-3n-hsw-x710
- container_memif-3n-hsw-xl710
- container_memif-3n-skx-x710
- container_memif-2n-skx-x710
-
-..
container_memif-2n-skx-xxv710
container_memif-2n-skx-xxv710
+ container_memif-3n-skx-xxv710
+ container_memif-2n-clx-xxv710
+ container_memif-2n-clx-cx556a
+ container_memif-3n-tsh-x520