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Report: Add 2n-clx
[csit.git]
/
docs
/
report
/
vpp_performance_tests
/
packet_latency_graphs
/
ip4_tunnels.rst
diff --git
a/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
b/docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
index
ac514d4
..
6ff5d67
100644
(file)
--- a/
docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
+++ b/
docs/report/vpp_performance_tests/packet_latency_graphs/ip4_tunnels.rst
@@
-13,9
+13,10
@@
thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s)
placement.
CSIT source code for the test cases used for plots can be found in
placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls
1908
>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls
2001
>`_.
.. toctree::
ip4_tunnels-3n-skx-xxv710
ip4_tunnels-3n-hsw-xl710
.. toctree::
ip4_tunnels-3n-skx-xxv710
ip4_tunnels-3n-hsw-xl710
+ ip4_tunnels-3n-tsh-x520