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CSIT-618 Update release report datapoints
[csit.git]
/
docs
/
report
/
vpp_performance_tests
/
packet_latency_graphs
/
l2.rst
diff --git
a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
index
d6e76a7
..
508d33c
100644
(file)
--- a/
docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
+++ b/
docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
@@
-13,13
+13,15
@@
VPP packet latency in 1t1c setup (1thread, 1core) is presented in the graph belo
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-1t1c-l2-sel1-ndrdisc-lat50.html"></iframe>
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-1t1c-l2-sel1-ndrdisc-lat50.html"></iframe>
-*Figure 1a. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet Switching.*
+*Figure 1a. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet
+Switching (base).*
.. raw:: html
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-1t1c-l2-sel2-ndrdisc-lat50.html"></iframe>
.. raw:: html
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-1t1c-l2-sel2-ndrdisc-lat50.html"></iframe>
-*Figure 1b. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet Switching.*
+*Figure 1b. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet
+Switching (feature).*
CSIT source code for the test cases used for above plots can be found in CSIT
git repository:
CSIT source code for the test cases used for above plots can be found in CSIT
git repository:
@@
-33,13
+35,15
@@
VPP packet latency in 2t2c setup (2thread, 2core) is presented in the graph belo
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-2t2c-l2-sel1-ndrdisc-lat50.html"></iframe>
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-2t2c-l2-sel1-ndrdisc-lat50.html"></iframe>
-*Figure 2a. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet Switching.*
+*Figure 2a. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet
+Switching (base).*
.. raw:: html
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-2t2c-l2-sel2-ndrdisc-lat50.html"></iframe>
.. raw:: html
<iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-2t2c-l2-sel2-ndrdisc-lat50.html"></iframe>
-*Figure 2b. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet Switching.*
+*Figure 2b. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet
+Switching (feature).*
CSIT source code for the test cases used for above plots can be found in CSIT
git repository:
CSIT source code for the test cases used for above plots can be found in CSIT
git repository: