Report 1904.2: Configuration

[csit.git] / docs / report / vpp_performance_tests / packet_latency_graphs / l2.rst

diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
index 3aae134..66b1fa4 100644 (file)
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst
@@ -39,14 +39,16 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
 physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in

-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1810>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1901>`_.

 
 .. toctree::
 
 
 .. toctree::
 

+    l2-3n-skx-x710
+
+..

     l2-3n-hsw-x520
     l2-3n-hsw-x710
     l2-3n-hsw-xl710
     l2-3n-hsw-x520
     l2-3n-hsw-x710
     l2-3n-hsw-xl710

-    l2-3n-skx-x710

     l2-3n-skx-xxv710
     l2-2n-skx-x710
     l2-2n-skx-xxv710
     l2-3n-skx-xxv710
     l2-2n-skx-x710
     l2-2n-skx-xxv710