-This section provides a summary of VPP Phy-to-Phy L2 Ethernet switching
-performance illustrating packet latency measured at 50% of discovered NDR
-throughput rate. Latency is reported for VPP running in multiple
-configurations of VPP worker thread(s), a.k.a. VPP data plane thread (s), and
-their physical CPU core(s) placement.
-
-Title of each graph is a regex (regular expression) matching all plotted
-test case throughput measurements.
+This section includes summary graphs of VPP Phy-to-Phy packet latency
+with L2 Ethernet switching measured at 50% of discovered NDR throughput
+rate. Latency is reported for VPP running in multiple configurations of
+VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
+physical CPU core(s) placement.
+
+Results are generated from a single execution of CSIT NDR discovery
+test. Box plots are used to show the Minimum, Average and Maximum packet
+latency per test.
+
+*Title of each graph* is a regex (regular expression) matching all
+throughput test cases plotted on this graph, *X-axis labels* are indices
+of individual test suites executed by csit-vpp-perf-1704-all job that
+created result output file used as data source for the graph, *Y-axis
+labels* are measured packet Latency [uSec] values, and the *Graph
+legend* lists the plotted test suites and their indices. Latency is
+reported for concurrent symmetric bi-directional flows, separately for
+each direction: i) West-to-East: TGint1-to-SUT1-to-SUT2-to-TGint2, and
+ii) East-to-West: TGint2-to-SUT2-to-SUT1-to-TGint1.