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Report: configure rls2110
[csit.git]
/
docs
/
report
/
vpp_performance_tests
/
packet_throughput_graphs
/
container_memif.rst
diff --git
a/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
b/docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
index
c069cf6
..
2170d5e
100644
(file)
--- a/
docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
+++ b/
docs/report/vpp_performance_tests/packet_throughput_graphs/container_memif.rst
@@
-13,7
+13,7
@@
running in multiple configurations of VPP worker thread(s), a.k.a. VPP
data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls2
009
>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls2
110
>`_.
.. toctree::
.. toctree::
@@
-23,4
+23,3
@@
CSIT source code for the test cases used for plots can be found in
container_memif-2n-clx-cx556a
container_memif-2n-zn2-xxv710
container_memif-2n-zn2-cx556a
container_memif-2n-clx-cx556a
container_memif-2n-zn2-xxv710
container_memif-2n-zn2-cx556a
- container_memif-3n-tsh-x520