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Report: Add 2n-icx e810cq
[csit.git]
/
docs
/
report
/
vpp_performance_tests
/
throughput_speedup_multi_core
/
ip4_tunnels.rst
diff --git
a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
index
d37a44f
..
0183d9b
100644
(file)
--- a/
docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
+++ b/
docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
@@
-15,11
+15,16
@@
running in multiple configurations of VPP worker thread(s), a.k.a. VPP
data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2
001
>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2
210
>`_.
.. toctree::
.. toctree::
- ip4_tunnels-3n-skx-xxv710
- ip4_tunnels-3n-hsw-xl710
+ ip4_tunnels-2n-icx-xxv710
+ ip4_tunnels-2n-icx-e810cq
+ ip4_tunnels-3n-icx-xxv710
+ ip4_tunnels-3n-icx-e810xxv
+ ip4_tunnels-2n-clx-xxv710
+ ip4_tunnels-2n-zn2-xxv710
+ ip4_tunnels-3n-alt-xl710
ip4_tunnels-3n-tsh-x520
ip4_tunnels-3n-tsh-x520
- ip4_tunnels-3n-
dnv-x553
+ ip4_tunnels-3n-
snr-e822cq