- [dpdk_is_1702_or_1705=yes]
- [AC_MSG_RESULT([yes])],
- [dpdk_is_1702_or_1705=no]
- [AC_MSG_RESULT([no])]
+ [
+ #Define Implementer Ids here
+ implementer_id_cavium=0x43
+
+ #Define CPU Ids here
+ cpu_id_cavium_thunderx_cn88xx=0x0a1
+ cpu_id_cavium_thunderx2_cn99xx=0x0af
+
+ implementer=read_midr_implementer()
+ cpuid=read_midr_cpuid()
+
+ AC_MSG_CHECKING([for implementerid/cpuid to set log2_cache_line_size])
+
+ # Switch case to map log2_cache_line_size for implementer/cpuid combination.
+ # Default case of Switch sets log2_cache_line_size to 6
+ AS_CASE($implementer,
+ #Switch Case for Cavium SoC's
+ [$implementer_id_cavium],
+ [AS_CASE($cpuid,
+ #Only ThunderX2 is 64B. Remaining chips are 128B
+ [$cpu_id_cavium_thunderx2_cn99xx],
+ [AC_MSG_RESULT([Cavium/ThunderX2]);log2_cache_line_size=6],
+ [$cpu_id_cavium_thunderx_cn88xx],
+ [AC_MSG_RESULT([Cavium/ThunderX]);log2_cache_line_size=7],
+ [log2_cache_line_size=7;AC_MSG_RESULT([Cavium/OCTEONTx($cpuid)])]
+ )],
+ #Add implementer specific case here:
+
+ #Default case: 64B for all SoC's
+ [log2_cache_line_size=6;AC_MSG_RESULT([$implementer/$cpuid])]
+ )
+ AC_MSG_NOTICE([log2_cache_line_size deduced as $log2_cache_line_size])
+ ]