a DUT application (e.g. VPP, DPDK), are determined by testing it in the
same test environment, to avoid test environment changes clouding the
picture.
+To beter distinguish impact of test environment changes,
+we also execute tests without any SUT (just with TRex TG sending packets
+over a link looping back to TG).
A mirror approach is introduced to determine benchmarking anomalies due
to the test environment change. This is achieved by testing the same DUT
`CSIT <https://git.fd.io/csit/tree/?h=rls2110>`_).
- Intel NIC 700/800 series firmware upgrade based on DPDK compatibility
- matrix: `depends on testbed type <https://gerrit.fd.io/r/c/csit/+/33311>`_.
-
-To identify performance changes due to VPP code development between previous
-and current VPP release version, both have been tested in CSIT environment of
-latest version and compared against each other. All substantial progressions and
-regressions have been marked up with RCA analysis. See
-:ref:`vpp_throughput_comparisons` and :ref:`vpp_known_issues`.
-
-Physical Testbeds
------------------
-
-FD.io CSIT performance tests are executed in physical testbeds hosted by
-:abbr:`LF (Linux Foundation)` for FD.io project. Two physical testbed
-topology types are used:
-
-- **3-Node Topology**: Consisting of two servers acting as SUTs
- (Systems Under Test) and one server as TG (Traffic Generator), all
- connected in ring topology.
-- **2-Node Topology**: Consisting of one server acting as SUTs and one
- server as TG both connected in ring topology.
-
-Tested SUT servers are based on a range of processors including Intel
-Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm,
-Intel Atom. More detailed description is provided in
-:ref:`tested_physical_topologies`. Tested logical topologies are
-described in :ref:`tested_logical_topologies`.
+ matrix.
+- Ver. 9 associated with CSIT rls2202 branch (`HW
+ <https://git.fd.io/csit/tree/docs/lab?h=rls2202>`_, `Linux
+ <https://s3-docs.fd.io/csit/rls2202/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_,
+ `TRex
+ <https://s3-docs.fd.io/csit/rls2202/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_,
+ `CSIT <https://git.fd.io/csit/tree/?h=rls2202>`_).
-Server Specifications
----------------------
+ - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility
+ matrix.
+- Ver. 10 associated with CSIT rls2206 branch (`HW
+ <https://git.fd.io/csit/tree/docs/lab?h=rls2206>`_, `Linux
+ <https://s3-docs.fd.io/csit/rls2206/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_,
+ `TRex
+ <https://s3-docs.fd.io/csit/rls2206/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_,
+ `CSIT <https://git.fd.io/csit/tree/?h=rls2206>`_).
-Complete technical specifications of compute servers used in CSIT
-physical testbeds are maintained in FD.io CSIT repository:
-`FD.io CSIT testbeds - Xeon Cascade Lake`_,
-`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_.
+ - Intel NIC 700/800 series firmware upgrade based on DPDK compatibility
+ matrix.
+ - Mellanox 556A series firmware upgrade based on DPDK compatibility
+ matrix.
+ - Intel IceLake all core turbo frequency turned off. Current base frequency
+ is 2.6Ghz.
\ No newline at end of file