Report 2005: Add data, review graphs

[csit.git] / docs / report / introduction / test_environment_intro.rst

diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst
index 7763e9d..7c4d5df 100644 (file)
--- a/docs/report/introduction/test_environment_intro.rst
+++ b/docs/report/introduction/test_environment_intro.rst
@@ -1,5 +1,3 @@
-.. _test_environment:
-
 Test Environment
 ================
 
@@ -17,8 +15,8 @@ topology types are used:
   server as TG both connected in ring topology.
 
 Tested SUT servers are based on a range of processors including Intel
-Xeon Haswell-SP, Intel Xeon Skylake-SP, Arm, Intel Atom. More detailed
-description is provided in
+Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, Intel
+Atom. More detailed description is provided in
 :ref:`tested_physical_topologies`. Tested logical topologies are
 described in :ref:`tested_logical_topologies`.
 
@@ -26,36 +24,7 @@ Server Specifications
 ---------------------
 
 Complete technical specifications of compute servers used in CSIT
-physical testbeds are maintained on FD.io wiki pages: `CSIT/Testbeds:
-Xeon Hsw, VIRL
-<https://wiki.fd.io/view/CSIT/Testbeds:_Xeon_Hsw,_VIRL.#FD.io_CSIT_testbeds_-_Xeon_Haswell.2C_VIRL>`_
-and `CSIT Testbeds: Xeon Skx, Arm, Atom
-<https://wiki.fd.io/view/CSIT/Testbeds:_Xeon_Skx,_Arm,_Atom.#Server_Specification>`_.
-
-Pre-Test Server Calibration
----------------------------
-
-Number of SUT server sub-system runtime parameters have been identified
-as impacting data plane performance tests. Calibrating those parameters
-is part of FD.io CSIT pre-test activities, and includes measuring and
-reporting following:
-
-#. System level core jitter – measure duration of core interrupts by
-   Linux in clock cycles and how often interrupts happen. Using
-   `CPU core jitter tool <https://git.fd.io/pma_tools/tree/jitter>`_.
-
-#. Memory bandwidth – measure bandwidth with `Intel MLC tool
-   <https://software.intel.com/en-us/articles/intelr-memory-latency-checker>`_.
-
-#. Memory latency – measure memory latency with Intel MLC tool.
-
-#. Cache latency at all levels (L1, L2, and Last Level Cache) – measure
-   cache latency with Intel MLC tool.
-
-Measured values of listed parameters are especially important for
-repeatable zero packet loss throughput measurements across multiple
-system instances. Generally they come useful as a background data for
-comparing data plane performance results across disparate servers.
-
-Following sections include measured calibration data for Intel Xeon
-Haswell and Intel Xeon Skylake testbeds.
+physical testbeds are maintained in FD.io CSIT repository:
+`FD.io CSIT testbeds - Xeon Cascade Lake`_,
+`FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and
+`FD.io CSIT Testbeds - Xeon Haswell`_.