data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls1908>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls2001>`_.
.. toctree::
ip4-2n-skx-x710
ip4-3n-skx-xxv710
ip4-3n-skx-x710
+ ip4-2n-clx-xxv710
+ ip4-2n-clx-x710
+ ip4-2n-clx-cx556a
ip4-3n-hsw-xl710
ip4-3n-tsh-x520
+
+..
+ ip4-2n-dnv-x553
+ ip4-3n-dnv-x553