data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls2202>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4?h=rls2206>`_.
.. toctree::
ip4-2n-clx-xxv710
ip4-2n-clx-x710
ip4-2n-clx-cx556a
+ ip4-2n-clx-e810cq
ip4-2n-zn2-xxv710
ip4-2n-zn2-x710
ip4-2n-zn2-cx556a
+ ip4-3n-alt-xl710
ip4-3n-tsh-x520
ip4-2n-tx2-xl710
ip4-2n-dnv-x553
ip4-3n-dnv-x553
ip4-2n-aws-nitro50g
- ip4-3n-aws-nitro50g