data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls1901>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2210>`_.
.. toctree::
- ip4_tunnels-3n-hsw-x520
- ip4_tunnels-3n-hsw-x710
- ip4_tunnels-3n-skx-x710
+ ip4_tunnels-2n-icx-xxv710
+ ip4_tunnels-3n-icx-xxv710
+ ip4_tunnels-3n-icx-e810xxv
+ ip4_tunnels-2n-clx-xxv710
+ ip4_tunnels-2n-zn2-xxv710
+ ip4_tunnels-3n-alt-xl710
+ ip4_tunnels-3n-tsh-x520
+ ip4_tunnels-3n-dnv-x553
+ ip4_tunnels-3n-snr-e822cq