data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls2001>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls2101>`_.
.. toctree::
l2-2n-skx-xxv710
l2-2n-skx-x710
+ l2-3n-skx-xxv710
+ l2-3n-skx-x710
l2-2n-clx-xxv710
l2-2n-clx-x710
l2-2n-clx-cx556a
+ l2-2n-zn2-xxv710
+ l2-2n-zn2-x710
+ l2-2n-zn2-cx556a
l2-3n-hsw-xl710
l2-3n-tsh-x520
+ l2-2n-tx2-xl710
l2-2n-dnv-x553
l2-3n-dnv-x553
-
-..
- l2-3n-skx-xxv710
- l2-3n-skx-x710