data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1908>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls2001>`_.
.. toctree::
srv6-3n-skx-xxv710
srv6-3n-hsw-xl710
srv6-3n-tsh-x520
+
+..
srv6-3n-dnv-x553