data plane thread(s), and their physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2001>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2101>`_.
.. toctree::
+ ip4_tunnels-2n-skx-xxv710
+ ip4_tunnels-2n-clx-xxv710
+ ip4_tunnels-2n-zn2-xxv710
ip4_tunnels-3n-skx-xxv710
ip4_tunnels-3n-hsw-xl710
ip4_tunnels-3n-tsh-x520