New upstream version 17.11.1

[deb_dpdk.git] / drivers / crypto / qat / qat_adf / qat_algs_build_desc.c

diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 154e1dd..26f854c 100644 (file)
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -17,7 +17,7 @@
  *  qat-linux@intel.com
  *
  *  BSD LICENSE
- *  Copyright(c) 2015-2016 Intel Corporation.
+ *  Copyright(c) 2015-2017 Intel Corporation.
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
  *  are met:
@@ -121,6 +121,12 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
        case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
                return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,
                                                QAT_HW_DEFAULT_ALIGNMENT);
+       case ICP_QAT_HW_AUTH_ALGO_NULL:
+               return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,
+                                               QAT_HW_DEFAULT_ALIGNMENT);
+       case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
+               return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ,
+                                               QAT_HW_DEFAULT_ALIGNMENT);
        case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
                /* return maximum state1 size in this case */
                return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -353,6 +359,11 @@ static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
 
                in = rte_zmalloc("working mem for key",
                                ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
+               if (in == NULL) {
+                       PMD_DRV_LOG(ERR, "Failed to alloc memory");
+                       return -ENOMEM;
+               }
+
                rte_memcpy(in, qat_aes_xcbc_key_seed,
                                ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
                for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
@@ -383,6 +394,11 @@ static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
                                ICP_QAT_HW_GALOIS_E_CTR0_SZ);
                in = rte_zmalloc("working mem for key",
                                ICP_QAT_HW_GALOIS_H_SZ, 16);
+               if (in == NULL) {
+                       PMD_DRV_LOG(ERR, "Failed to alloc memory");
+                       return -ENOMEM;
+               }
+
                memset(in, 0, ICP_QAT_HW_GALOIS_H_SZ);
                if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
                        &enc_key) != 0) {
@@ -603,6 +619,7 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
                cipher_cd_ctrl->cipher_state_sz =
                        ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
                qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;
+               cdesc->min_qat_dev_gen = QAT_GEN2;
        } else {
                total_key_size = cipherkeylen;
                cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
@@ -661,7 +678,7 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
 int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
                                                uint8_t *authkey,
                                                uint32_t authkeylen,
-                                               uint32_t add_auth_data_length,
+                                               uint32_t aad_length,
                                                uint32_t digestsize,
                                                unsigned int operation)
 {
@@ -810,13 +827,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
                 * in big-endian format. This field is 8 bytes
                 */
                auth_param->u2.aad_sz =
-                               RTE_ALIGN_CEIL(add_auth_data_length, 16);
+                               RTE_ALIGN_CEIL(aad_length, 16);
                auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
 
                aad_len = (uint32_t *)(cdesc->cd_cur_ptr +
                                        ICP_QAT_HW_GALOIS_128_STATE1_SZ +
                                        ICP_QAT_HW_GALOIS_H_SZ);
-               *aad_len = rte_bswap32(add_auth_data_length);
+               *aad_len = rte_bswap32(aad_length);
+               cdesc->aad_len = aad_length;
                break;
        case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
                qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;
@@ -837,8 +855,7 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
                                0, ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ);
                cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
                                authkeylen + ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ;
-               auth_param->hash_state_sz =
-                               RTE_ALIGN_CEIL(add_auth_data_length, 16) >> 3;
+               auth_param->hash_state_sz = ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;
                break;
        case ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:
                hash->auth_config.config =
@@ -854,8 +871,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
                memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
                cdesc->cd_cur_ptr += state1_size + state2_size
                        + ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;
-               auth_param->hash_state_sz =
-                               RTE_ALIGN_CEIL(add_auth_data_length, 16) >> 3;
+               auth_param->hash_state_sz = ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
+               cdesc->min_qat_dev_gen = QAT_GEN2;
 
                break;
        case ICP_QAT_HW_AUTH_ALGO_MD5:
@@ -868,6 +885,34 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
                state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
                break;
        case ICP_QAT_HW_AUTH_ALGO_NULL:
+               state1_size = qat_hash_get_state1_size(
+                               ICP_QAT_HW_AUTH_ALGO_NULL);
+               state2_size = ICP_QAT_HW_NULL_STATE2_SZ;
+               break;
+       case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
+               qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;
+               state1_size = qat_hash_get_state1_size(
+                               ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC);
+               state2_size = ICP_QAT_HW_AES_CBC_MAC_KEY_SZ +
+                               ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ;
+
+               if (aad_length > 0) {
+                       aad_length += ICP_QAT_HW_CCM_AAD_B0_LEN +
+                               ICP_QAT_HW_CCM_AAD_LEN_INFO;
+                       auth_param->u2.aad_sz =
+                                       RTE_ALIGN_CEIL(aad_length,
+                                       ICP_QAT_HW_CCM_AAD_ALIGNMENT);
+               } else {
+                       auth_param->u2.aad_sz = ICP_QAT_HW_CCM_AAD_B0_LEN;
+               }
+
+               cdesc->aad_len = aad_length;
+               hash->auth_counter.counter = 0;
+
+               hash_cd_ctrl->outer_prefix_sz = digestsize;
+               auth_param->hash_state_sz = digestsize;
+
+               memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
                break;
        case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
                state1_size = qat_hash_get_state1_size(