-/*-
+/* SPDX-License-Identifier: BSD-3-Clause
* Copyright (c) 2007-2013 Broadcom Corporation.
*
* Eric Davis <edavis@broadcom.com>
* Gary Zambrano <zambrano@broadcom.com>
*
* Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
- * Copyright (c) 2015 QLogic Corporation.
+ * Copyright (c) 2015-2018 Cavium Inc.
* All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.bnx2x_pmd for copyright and licensing details.
+ * www.cavium.com
*/
#ifndef __BNX2X_H__
#include <rte_byteorder.h>
#include <rte_spinlock.h>
+#include <rte_bus_pci.h>
+#include <rte_io.h>
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
#ifndef __LITTLE_ENDIAN
/* Used to manage DMA allocations. */
struct bnx2x_dma {
struct bnx2x_softc *sc;
- phys_addr_t paddr;
+ rte_iova_t paddr;
void *vaddr;
int nseg;
char msg[RTE_MEMZONE_NAMESIZE - 6];
struct bnx2x_dma sb_dma;
union bnx2x_host_hc_status_block status_block;
- phys_addr_t tx_desc_mapping;
+ rte_iova_t tx_desc_mapping;
- phys_addr_t rx_desc_mapping;
- phys_addr_t rx_comp_mapping;
+ rte_iova_t rx_desc_mapping;
+ rte_iova_t rx_comp_mapping;
uint16_t *sb_index_values;
uint16_t *sb_running_index;
struct hw_context {
struct bnx2x_dma vcxt_dma;
union cdu_context *vcxt;
- //phys_addr_t cxt_mapping;
+ //rte_iova_t cxt_mapping;
size_t size;
};
uint32_t phy_addr;
+ /* Used to synchronize phy accesses. */
+ rte_spinlock_t phy_mtx;
+ char phy_mtx_name[32];
+
+#define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
+#define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
+
/*
* MCP scratchpad address for port specific statistics.
* The device is responsible for writing statistcss
/* Device information data structure. */
struct bnx2x_devinfo {
+#if 1
+#define NAME_SIZE 128
+ char name[NAME_SIZE];
+#endif
/* PCIe info */
uint16_t vendor_id;
uint16_t device_id;
#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
/* device ids */
+#define CHIP_NUM_57710 0x164e
#define CHIP_NUM_57711 0x164f
#define CHIP_NUM_57711E 0x1650
#define CHIP_NUM_57712 0x1662
#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
+#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
+#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
uint32_t gz_outlen;
#define GUNZIP_BUF(sc) (sc->gz_buf)
#define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
-#define GUNZIP_PHYS(sc) (phys_addr_t)(sc->gz_buf_dma.paddr)
+#define GUNZIP_PHYS(sc) (rte_iova_t)(sc->gz_buf_dma.paddr)
#define FW_BUF_SIZE 0x40000
struct raw_op *init_ops;
*/
int fw_stats_req_size;
struct bnx2x_fw_stats_req *fw_stats_req;
- phys_addr_t fw_stats_req_mapping;
+ rte_iova_t fw_stats_req_mapping;
/*
* FW statistics data shortcut (points at the beginning of fw_stats
* buffer + fw_stats_req_size).
*/
int fw_stats_data_size;
struct bnx2x_fw_stats_data *fw_stats_data;
- phys_addr_t fw_stats_data_mapping;
+ rte_iova_t fw_stats_data_mapping;
/* tracking a pending STAT_QUERY ramrod */
uint16_t stats_pending;
#define FUNC_FLG_LEADING 0x0020 /* PF only */
struct bnx2x_func_init_params {
- phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
- phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
+ rte_iova_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
+ rte_iova_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
uint16_t func_flgs;
uint16_t func_id; /* abs function id */
uint16_t pf_id;
static inline void
bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
{
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
(unsigned long)offset, val);
- *((volatile uint8_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+ rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
}
static inline void
{
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 2) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx",
(unsigned long)offset);
#endif
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x",
(unsigned long)offset, val);
- *((volatile uint16_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+ rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
+
}
static inline void
{
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 4) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx",
(unsigned long)offset);
#endif
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
- *((volatile uint32_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+ rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
}
static inline uint8_t
{
uint8_t val;
- val = (uint8_t)(*((volatile uint8_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
+ val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
(unsigned long)offset, val);
return val;
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 2) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx",
(unsigned long)offset);
#endif
- val = (uint16_t)(*((volatile uint16_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+ val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
return val;
#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
if ((offset % 4) != 0)
- PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
+ PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx",
(unsigned long)offset);
#endif
- val = (uint32_t)(*((volatile uint32_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
- PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
+ val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
return val;
#define REG_RD_DMAE(sc, offset, valp, len32) \
do { \
(void)bnx2x_read_dmae(sc, offset, len32); \
- (void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
+ rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
} while (0)
#define REG_WR_DMAE(sc, offset, valp, len32) \
do { \
- (void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
+ rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
(void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
} while (0)
#define DPM_TRIGGER_TYPE 0x40
/* Doorbell macro */
-#define BNX2X_DB_WRITE(db_bar, val) \
- *((volatile uint32_t *)(db_bar)) = (val)
+#define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))
-#define BNX2X_DB_READ(db_bar) \
- *((volatile uint32_t *)(db_bar))
+#define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar)
#define DOORBELL_ADDR(sc, offset) \
(volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
uint8_t comp_type);
void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
-void bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr,
+void bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr,
uint32_t dst_addr, uint32_t len32);
void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
uint32_t cid);
int bnx2x_complete_sp(struct bnx2x_softc *sc);
int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
void bnx2x_periodic_callout(struct bnx2x_softc *sc);
+void bnx2x_periodic_stop(void *param);
int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
void bnx2x_vf_close(struct bnx2x_softc *sc);
bnx2x_vf_set_rx_mode(sc);
}
} else {
- PMD_DRV_LOG(NOTICE, "Card is not ready to change mode");
+ PMD_DRV_LOG(NOTICE, sc, "Card is not ready to change mode");
}
}
static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
void *val, uint8_t size)
{
- if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
- PMD_DRV_LOG(ERR, "Can't read from PCI config space");
+ if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
+ PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space");
return ENXIO;
}
{
uint16_t val16 = val;
- if (rte_eal_pci_write_config(sc->pci_dev, &val16,
+ if (rte_pci_write_config(sc->pci_dev, &val16,
sizeof(val16), addr) <= 0) {
- PMD_DRV_LOG(ERR, "Can't write to PCI config space");
+ PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
return ENXIO;
}
static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
{
uint32_t val32 = val;
- if (rte_eal_pci_write_config(sc->pci_dev, &val32,
+ if (rte_pci_write_config(sc->pci_dev, &val32,
sizeof(val32), addr) <= 0) {
- PMD_DRV_LOG(ERR, "Can't write to PCI config space");
+ PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
return ENXIO;
}
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