/* enable emac and not bmac */
REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
-#ifdef ELINK_INCLUDE_EMUL
- /* for paladium */
- if (CHIP_REV_IS_EMUL(sc)) {
- /* Use lane 1 (of lanes 0-3) */
- REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
- REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
- }
- /* for fpga */
- else
-#endif
-#ifdef ELINK_INCLUDE_FPGA
- if (CHIP_REV_IS_FPGA(sc)) {
- /* Use lane 1 (of lanes 0-3) */
- PMD_DRV_LOG(DEBUG, "elink_emac_enable: Setting FPGA");
-
- REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);
- REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
- } else
-#endif
- /* ASIC */
if (vars->phy_flags & PHY_XGXS_FLAG) {
uint32_t ser_lane = ((params->lane_config &
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
EMAC_TX_MODE_RESET);
-#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
- if (CHIP_REV_IS_SLOW(sc)) {
- /* config GMII mode */
- val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
- elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
- (val | EMAC_MODE_PORT_GMII));
- } else { /* ASIC */
-#endif
- /* pause enable/disable */
- elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
- EMAC_RX_MODE_FLOW_EN);
+ /* pause enable/disable */
+ elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
- elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
- (EMAC_TX_MODE_EXT_PAUSE_EN |
- EMAC_TX_MODE_FLOW_EN));
- if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
- if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
- elink_bits_en(sc, emac_base +
- EMAC_REG_EMAC_RX_MODE,
- EMAC_RX_MODE_FLOW_EN);
-
- if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
- elink_bits_en(sc, emac_base +
- EMAC_REG_EMAC_TX_MODE,
- (EMAC_TX_MODE_EXT_PAUSE_EN |
- EMAC_TX_MODE_FLOW_EN));
- } else
- elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
- EMAC_TX_MODE_FLOW_EN);
-#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
- }
-#endif
+ elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+ (EMAC_TX_MODE_EXT_PAUSE_EN |
+ EMAC_TX_MODE_FLOW_EN));
+ if (!(params->feature_config_flags &
+ ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
+ if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
+ elink_bits_en(sc, emac_base +
+ EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
+
+ if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
+ elink_bits_en(sc, emac_base +
+ EMAC_REG_EMAC_TX_MODE,
+ (EMAC_TX_MODE_EXT_PAUSE_EN |
+ EMAC_TX_MODE_FLOW_EN));
+ } else
+ elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
+ EMAC_TX_MODE_FLOW_EN);
/* KEEP_VLAN_TAG, promiscuous */
val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
-#ifdef ELINK_INCLUDE_EMUL
- if (CHIP_REV_IS_EMUL(sc)) {
- /* Take the BigMac out of reset */
- REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
- (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
-
- /* Enable access for bmac registers */
- REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
- } else
-#endif
- REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
+ REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
vars->mac_type = ELINK_MAC_TYPE_EMAC;
return ELINK_STATUS_OK;
wb_data[1] = 0;
REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
wb_data, 2);
-#ifdef ELINK_INCLUDE_EMUL
- /* Fix for emulation */
- if (CHIP_REV_IS_EMUL(sc)) {
- wb_data[0] = 0xf000;
- wb_data[1] = 0;
- REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
- wb_data, 2);
- }
-#endif
return ELINK_STATUS_OK;
}
elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
}
-static void elink_warpcore_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint32_t serdes_net_if;
case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
if (vars->line_speed != ELINK_SPEED_20000) {
PMD_DRV_LOG(DEBUG, "Speed not supported yet");
- return;
+ return 0;
}
PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS");
elink_warpcore_set_20G_DXGXS(sc, phy, lane);
PMD_DRV_LOG(DEBUG,
"Unsupported Serdes Net Interface 0x%x",
serdes_net_if);
- return;
+ return 0;
}
}
/* Take lane out of reset after configuration is finished */
elink_warpcore_reset_lane(sc, phy, 0);
PMD_DRV_LOG(DEBUG, "Exit config init");
+
+ return 0;
}
static void elink_warpcore_link_reset(struct elink_phy *phy,
return ELINK_STATUS_OK;
}
-static elink_status_t elink_link_settings_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_link_settings_status(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
return rc;
}
-static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t lane;
}
}
-static void elink_xgxs_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
(params->loopback_mode == ELINK_LOOPBACK_XGXS));
elink_initialize_sgmii_process(phy, params, vars);
}
+
+ return 0;
}
static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
}
}
-static elink_status_t elink_format_ver(uint32_t num, uint8_t * str,
- uint16_t * len)
+static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
+ uint16_t * len)
{
uint8_t *str_ptr = str;
uint32_t mask = 0xf0000000;
return ELINK_STATUS_OK;
}
-static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
- uint8_t * str, uint16_t * len)
+static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
+ uint8_t * str, uint16_t * len)
{
str[0] = '\0';
(*len)--;
params, mode);
}
}
-#ifdef ELINK_INCLUDE_EMUL
- if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
- return rc;
-#endif
switch (mode) {
case ELINK_LED_MODE_FRONT_PANEL_OFF:
}
}
-static elink_status_t elink_8073_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_8073_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint16_t val = 0, tmp1;
/******************************************************************/
/* BNX2X8705 PHY SECTION */
/******************************************************************/
-static elink_status_t elink_8705_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
+static uint8_t elink_8705_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ __rte_unused struct elink_vars
*vars)
{
struct bnx2x_softc *sc = params->sc;
return ELINK_STATUS_OK;
}
-static elink_status_t elink_8706_read_status(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_8706_read_status(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
return elink_8706_8726_read_status(phy, params, vars);
}
return link_up;
}
-static elink_status_t elink_8726_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_8726_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726");
}
}
-static elink_status_t elink_8727_config_init(struct elink_phy *phy,
- struct elink_params *params,
- __rte_unused struct elink_vars
+static uint8_t elink_8727_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ __rte_unused struct elink_vars
*vars)
{
uint32_t tx_en_mode;
return ELINK_STATUS_OK;
}
-static elink_status_t elink_8481_config_init(struct elink_phy *phy,
+static uint8_t elink_8481_config_init(struct elink_phy *phy,
struct elink_params *params,
struct elink_vars *vars)
{
return reset_gpios;
}
-static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
- struct elink_params *params)
+static void elink_84833_hw_reset_phy(struct elink_phy *phy,
+ struct elink_params *params)
{
struct bnx2x_softc *sc = params->sc;
uint8_t reset_gpios;
MISC_REGISTERS_GPIO_OUTPUT_LOW);
DELAY(10);
PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios);
-
- return ELINK_STATUS_OK;
}
static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
}
#define PHY84833_CONSTANT_LATENCY 1193
-static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_848x3_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port, initialize = 1;
return link_up;
}
-static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
+static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
uint16_t * len)
{
elink_status_t status = ELINK_STATUS_OK;
}
}
-static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_54618se_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
struct bnx2x_softc *sc = params->sc;
uint8_t port;
MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
}
-static elink_status_t elink_7101_config_init(struct elink_phy *phy,
- struct elink_params *params,
- struct elink_vars *vars)
+static uint8_t elink_7101_config_init(struct elink_phy *phy,
+ struct elink_params *params,
+ struct elink_vars *vars)
{
uint16_t fw_ver1, fw_ver2, val;
struct bnx2x_softc *sc = params->sc;
return link_up;
}
-static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
- uint16_t * len)
+static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
+ uint16_t * len)
{
if (*len < 5)
return ELINK_STATUS_ERROR;
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) NULL,
- .read_status = (read_status_t) NULL,
- .link_reset = (link_reset_t) NULL,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) NULL,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = NULL,
+ .read_status = NULL,
+ .link_reset = NULL,
+ .config_loopback = NULL,
+ .format_fw_ver = NULL,
+ .hw_reset = NULL,
+ .set_link_led = NULL,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_serdes = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_xgxs_config_init,
- .read_status = (read_status_t) elink_link_settings_status,
- .link_reset = (link_reset_t) elink_int_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) NULL,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = elink_xgxs_config_init,
+ .read_status = elink_link_settings_status,
+ .link_reset = elink_int_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = NULL,
+ .hw_reset = NULL,
+ .set_link_led = NULL,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_xgxs = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_xgxs_config_init,
- .read_status = (read_status_t) elink_link_settings_status,
- .link_reset = (link_reset_t) elink_int_link_reset,
- .config_loopback = (config_loopback_t) elink_set_xgxs_loopback,
- .format_fw_ver = (format_fw_ver_t) NULL,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) elink_xgxs_specific_func
+ .config_init = elink_xgxs_config_init,
+ .read_status = elink_link_settings_status,
+ .link_reset = elink_int_link_reset,
+ .config_loopback = elink_set_xgxs_loopback,
+ .format_fw_ver = NULL,
+ .hw_reset = NULL,
+ .set_link_led = NULL,
+ .phy_specific_func = elink_xgxs_specific_func
};
static const struct elink_phy phy_warpcore = {
.speed_cap_mask = 0,
/* req_duplex = */ 0,
/* rsrv = */ 0,
- .config_init = (config_init_t) elink_warpcore_config_init,
- .read_status = (read_status_t) elink_warpcore_read_status,
- .link_reset = (link_reset_t) elink_warpcore_link_reset,
- .config_loopback = (config_loopback_t) elink_set_warpcore_loopback,
- .format_fw_ver = (format_fw_ver_t) NULL,
- .hw_reset = (hw_reset_t) elink_warpcore_hw_reset,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = elink_warpcore_config_init,
+ .read_status = elink_warpcore_read_status,
+ .link_reset = elink_warpcore_link_reset,
+ .config_loopback = elink_set_warpcore_loopback,
+ .format_fw_ver = NULL,
+ .hw_reset = elink_warpcore_hw_reset,
+ .set_link_led = NULL,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_7101 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_7101_config_init,
- .read_status = (read_status_t) elink_7101_read_status,
- .link_reset = (link_reset_t) elink_common_ext_link_reset,
- .config_loopback = (config_loopback_t) elink_7101_config_loopback,
- .format_fw_ver = (format_fw_ver_t) elink_7101_format_ver,
- .hw_reset = (hw_reset_t) elink_7101_hw_reset,
- .set_link_led = (set_link_led_t) elink_7101_set_link_led,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = elink_7101_config_init,
+ .read_status = elink_7101_read_status,
+ .link_reset = elink_common_ext_link_reset,
+ .config_loopback = elink_7101_config_loopback,
+ .format_fw_ver = elink_7101_format_ver,
+ .hw_reset = elink_7101_hw_reset,
+ .set_link_led = elink_7101_set_link_led,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_8073 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_8073_config_init,
- .read_status = (read_status_t) elink_8073_read_status,
- .link_reset = (link_reset_t) elink_8073_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_format_ver,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) elink_8073_specific_func
+ .config_init = elink_8073_config_init,
+ .read_status = elink_8073_read_status,
+ .link_reset = elink_8073_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_format_ver,
+ .hw_reset = NULL,
+ .set_link_led = NULL,
+ .phy_specific_func = elink_8073_specific_func
};
static const struct elink_phy phy_8705 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_8705_config_init,
- .read_status = (read_status_t) elink_8705_read_status,
- .link_reset = (link_reset_t) elink_common_ext_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_null_format_ver,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = elink_8705_config_init,
+ .read_status = elink_8705_read_status,
+ .link_reset = elink_common_ext_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_null_format_ver,
+ .hw_reset = NULL,
+ .set_link_led = NULL,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_8706 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_8706_config_init,
- .read_status = (read_status_t) elink_8706_read_status,
- .link_reset = (link_reset_t) elink_common_ext_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_format_ver,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = elink_8706_config_init,
+ .read_status = elink_8706_read_status,
+ .link_reset = elink_common_ext_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_format_ver,
+ .hw_reset = NULL,
+ .set_link_led = NULL,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_8726 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_8726_config_init,
- .read_status = (read_status_t) elink_8726_read_status,
- .link_reset = (link_reset_t) elink_8726_link_reset,
- .config_loopback = (config_loopback_t) elink_8726_config_loopback,
- .format_fw_ver = (format_fw_ver_t) elink_format_ver,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) NULL,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = elink_8726_config_init,
+ .read_status = elink_8726_read_status,
+ .link_reset = elink_8726_link_reset,
+ .config_loopback = elink_8726_config_loopback,
+ .format_fw_ver = elink_format_ver,
+ .hw_reset = NULL,
+ .set_link_led = NULL,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_8727 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_8727_config_init,
- .read_status = (read_status_t) elink_8727_read_status,
- .link_reset = (link_reset_t) elink_8727_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_format_ver,
- .hw_reset = (hw_reset_t) elink_8727_hw_reset,
- .set_link_led = (set_link_led_t) elink_8727_set_link_led,
- .phy_specific_func = (phy_specific_func_t) elink_8727_specific_func
+ .config_init = elink_8727_config_init,
+ .read_status = elink_8727_read_status,
+ .link_reset = elink_8727_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_format_ver,
+ .hw_reset = elink_8727_hw_reset,
+ .set_link_led = elink_8727_set_link_led,
+ .phy_specific_func = elink_8727_specific_func
};
static const struct elink_phy phy_8481 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_8481_config_init,
- .read_status = (read_status_t) elink_848xx_read_status,
- .link_reset = (link_reset_t) elink_8481_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
- .hw_reset = (hw_reset_t) elink_8481_hw_reset,
- .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
- .phy_specific_func = (phy_specific_func_t) NULL
+ .config_init = elink_8481_config_init,
+ .read_status = elink_848xx_read_status,
+ .link_reset = elink_8481_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_848xx_format_ver,
+ .hw_reset = elink_8481_hw_reset,
+ .set_link_led = elink_848xx_set_link_led,
+ .phy_specific_func = NULL
};
static const struct elink_phy phy_84823 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_848x3_config_init,
- .read_status = (read_status_t) elink_848xx_read_status,
- .link_reset = (link_reset_t) elink_848x3_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
- .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func
+ .config_init = elink_848x3_config_init,
+ .read_status = elink_848xx_read_status,
+ .link_reset = elink_848x3_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_848xx_format_ver,
+ .hw_reset = NULL,
+ .set_link_led = elink_848xx_set_link_led,
+ .phy_specific_func = elink_848xx_specific_func
};
static const struct elink_phy phy_84833 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_848x3_config_init,
- .read_status = (read_status_t) elink_848xx_read_status,
- .link_reset = (link_reset_t) elink_848x3_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
- .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy,
- .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
- .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func
+ .config_init = elink_848x3_config_init,
+ .read_status = elink_848xx_read_status,
+ .link_reset = elink_848x3_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_848xx_format_ver,
+ .hw_reset = elink_84833_hw_reset_phy,
+ .set_link_led = elink_848xx_set_link_led,
+ .phy_specific_func = elink_848xx_specific_func
};
static const struct elink_phy phy_84834 = {
.speed_cap_mask = 0,
.req_duplex = 0,
.rsrv = 0,
- .config_init = (config_init_t) elink_848x3_config_init,
- .read_status = (read_status_t) elink_848xx_read_status,
- .link_reset = (link_reset_t) elink_848x3_link_reset,
- .config_loopback = (config_loopback_t) NULL,
- .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,
- .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy,
- .set_link_led = (set_link_led_t) elink_848xx_set_link_led,
- .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func
+ .config_init = elink_848x3_config_init,
+ .read_status = elink_848xx_read_status,
+ .link_reset = elink_848x3_link_reset,
+ .config_loopback = NULL,
+ .format_fw_ver = elink_848xx_format_ver,
+ .hw_reset = elink_84833_hw_reset_phy,
+ .set_link_led = elink_848xx_set_link_led,
+ .phy_specific_func = elink_848xx_specific_func
};
static const struct elink_phy phy_54618se = {
.speed_cap_mask = 0,
/* req_duplex = */ 0,
/* rsrv = */ 0,
- .config_init = (config_init_t) elink_54618se_config_init,
- .read_status = (read_status_t) elink_54618se_read_status,
- .link_reset = (link_reset_t) elink_54618se_link_reset,
- .config_loopback = (config_loopback_t) elink_54618se_config_loopback,
- .format_fw_ver = (format_fw_ver_t) NULL,
- .hw_reset = (hw_reset_t) NULL,
- .set_link_led = (set_link_led_t) elink_5461x_set_link_led,
- .phy_specific_func = (phy_specific_func_t) elink_54618se_specific_func
+ .config_init = elink_54618se_config_init,
+ .read_status = elink_54618se_read_status,
+ .link_reset = elink_54618se_link_reset,
+ .config_loopback = elink_54618se_config_loopback,
+ .format_fw_ver = NULL,
+ .hw_reset = NULL,
+ .set_link_led = elink_5461x_set_link_led,
+ .phy_specific_func = elink_54618se_specific_func
};
/*****************************************************************/
struct elink_phy *phy;
params->num_phys = 0;
PMD_DRV_LOG(DEBUG, "Begin phy probe");
-#ifdef ELINK_INCLUDE_EMUL
- if (CHIP_REV_IS_EMUL(sc))
- return ELINK_STATUS_OK;
-#endif
+
phy_config_swapped = params->multi_phy_config &
PORT_HW_CFG_PHY_SWAPPED_ENABLED;
return ELINK_STATUS_OK;
}
-#ifdef ELINK_INCLUDE_EMUL
-static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
- struct elink_vars *vars)
-{
- struct bnx2x_softc *sc = params->sc;
- vars->line_speed = params->req_line_speed[0];
- /* In case link speed is auto, set speed the highest as possible */
- if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
- if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
- vars->line_speed = ELINK_SPEED_2500;
- else if (elink_is_4_port_mode(sc))
- vars->line_speed = ELINK_SPEED_10000;
- else
- vars->line_speed = ELINK_SPEED_20000;
- }
- if (vars->line_speed < ELINK_SPEED_10000) {
- if ((params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
- PMD_DRV_LOG(DEBUG, "Invalid line speed %d while UMAC is"
- " disabled!", params->req_line_speed[0]);
- return ELINK_STATUS_ERROR;
- }
- switch (vars->line_speed) {
- case ELINK_SPEED_10:
- vars->link_status = ELINK_LINK_10TFD;
- break;
- case ELINK_SPEED_100:
- vars->link_status = ELINK_LINK_100TXFD;
- break;
- case ELINK_SPEED_1000:
- vars->link_status = ELINK_LINK_1000TFD;
- break;
- case ELINK_SPEED_2500:
- vars->link_status = ELINK_LINK_2500TFD;
- break;
- default:
- PMD_DRV_LOG(DEBUG, "Invalid line speed %d for UMAC",
- vars->line_speed);
- return ELINK_STATUS_ERROR;
- }
- vars->link_status |= LINK_STATUS_LINK_UP;
-
- if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
- elink_umac_enable(params, vars, 1);
- else
- elink_umac_enable(params, vars, 0);
- } else {
- /* Link speed >= 10000 requires XMAC enabled */
- if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
- PMD_DRV_LOG(DEBUG, "Invalid line speed %d while XMAC is"
- " disabled!", params->req_line_speed[0]);
- return ELINK_STATUS_ERROR;
- }
- /* Check link speed */
- switch (vars->line_speed) {
- case ELINK_SPEED_10000:
- vars->link_status = ELINK_LINK_10GTFD;
- break;
- case ELINK_SPEED_20000:
- vars->link_status = ELINK_LINK_20GTFD;
- break;
- default:
- PMD_DRV_LOG(DEBUG, "Invalid line speed %d for XMAC",
- vars->line_speed);
- return ELINK_STATUS_ERROR;
- }
- vars->link_status |= LINK_STATUS_LINK_UP;
- if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
- elink_xmac_enable(params, vars, 1);
- else
- elink_xmac_enable(params, vars, 0);
- }
- return ELINK_STATUS_OK;
-}
-
-static elink_status_t elink_init_emul(struct elink_params *params,
- struct elink_vars *vars)
-{
- struct bnx2x_softc *sc = params->sc;
- if (CHIP_IS_E3(sc)) {
- if (elink_init_e3_emul_mac(params, vars) != ELINK_STATUS_OK)
- return ELINK_STATUS_ERROR;
- } else {
- if (params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
- vars->line_speed = ELINK_SPEED_1000;
- vars->link_status = (LINK_STATUS_LINK_UP |
- ELINK_LINK_1000XFD);
- if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
- elink_emac_enable(params, vars, 1);
- else
- elink_emac_enable(params, vars, 0);
- } else {
- vars->line_speed = ELINK_SPEED_10000;
- vars->link_status = (LINK_STATUS_LINK_UP |
- ELINK_LINK_10GTFD);
- if (params->loopback_mode == ELINK_LOOPBACK_BMAC)
- elink_bmac_enable(params, vars, 1, 1);
- else
- elink_bmac_enable(params, vars, 0, 1);
- }
- }
- vars->link_up = 1;
- vars->duplex = DUPLEX_FULL;
- vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
-
- if (CHIP_IS_E1x(sc))
- elink_pbf_update(params, vars->flow_ctrl, vars->line_speed);
- /* Disable drain */
- REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
-
- /* update shared memory */
- elink_update_mng(params, vars->link_status);
- return ELINK_STATUS_OK;
-}
-#endif
-#ifdef ELINK_INCLUDE_FPGA
-static elink_status_t elink_init_fpga(struct elink_params *params,
- struct elink_vars *vars)
-{
- /* Enable on E1.5 FPGA */
- struct bnx2x_softc *sc = params->sc;
- vars->duplex = DUPLEX_FULL;
- vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
- vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | ELINK_FLOW_CTRL_RX);
- vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
- LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
- if (CHIP_IS_E3(sc)) {
- vars->line_speed = params->req_line_speed[0];
- switch (vars->line_speed) {
- case ELINK_SPEED_AUTO_NEG:
- vars->line_speed = ELINK_SPEED_2500;
- case ELINK_SPEED_2500:
- vars->link_status = ELINK_LINK_2500TFD;
- break;
- case ELINK_SPEED_1000:
- vars->link_status = ELINK_LINK_1000XFD;
- break;
- case ELINK_SPEED_100:
- vars->link_status = ELINK_LINK_100TXFD;
- break;
- case ELINK_SPEED_10:
- vars->link_status = ELINK_LINK_10TFD;
- break;
- default:
- PMD_DRV_LOG(DEBUG, "Invalid link speed %d",
- params->req_line_speed[0]);
- return ELINK_STATUS_ERROR;
- }
- vars->link_status |= LINK_STATUS_LINK_UP;
- if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
- elink_umac_enable(params, vars, 1);
- else
- elink_umac_enable(params, vars, 0);
- } else {
- vars->line_speed = ELINK_SPEED_10000;
- vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
- if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
- elink_emac_enable(params, vars, 1);
- else
- elink_emac_enable(params, vars, 0);
- }
- vars->link_up = 1;
-
- if (CHIP_IS_E1x(sc))
- elink_pbf_update(params, vars->flow_ctrl, vars->line_speed);
- /* Disable drain */
- REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
-
- /* Update shared memory */
- elink_update_mng(params, vars->link_status);
- return ELINK_STATUS_OK;
-}
-#endif
static void elink_init_bmac_loopback(struct elink_params *params,
struct elink_vars *vars)
{
ELINK_NIG_MASK_XGXS0_LINK10G |
ELINK_NIG_MASK_SERDES0_LINK_STATUS |
ELINK_NIG_MASK_MI_INT));
-#ifdef ELINK_INCLUDE_EMUL
- if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
-#endif
- elink_emac_init(params);
+ elink_emac_init(params);
if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
vars->link_status |= LINK_STATUS_PFC_ENABLED;
set_phy_vars(params, vars);
PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys);
-#ifdef ELINK_INCLUDE_FPGA
- if (CHIP_REV_IS_FPGA(sc)) {
- return elink_init_fpga(params, vars);
- } else
-#endif
-#ifdef ELINK_INCLUDE_EMUL
- if (CHIP_REV_IS_EMUL(sc)) {
- return elink_init_emul(params, vars);
- } else
-#endif
- switch (params->loopback_mode) {
- case ELINK_LOOPBACK_BMAC:
- elink_init_bmac_loopback(params, vars);
- break;
- case ELINK_LOOPBACK_EMAC:
- elink_init_emac_loopback(params, vars);
- break;
- case ELINK_LOOPBACK_XMAC:
- elink_init_xmac_loopback(params, vars);
- break;
- case ELINK_LOOPBACK_UMAC:
- elink_init_umac_loopback(params, vars);
- break;
- case ELINK_LOOPBACK_XGXS:
- case ELINK_LOOPBACK_EXT_PHY:
- elink_init_xgxs_loopback(params, vars);
- break;
- default:
- if (!CHIP_IS_E3(sc)) {
- if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
- elink_xgxs_deassert(params);
- else
- elink_serdes_deassert(sc, params->port);
- }
- elink_link_initialize(params, vars);
- DELAY(1000 * 30);
- elink_link_int_enable(params);
- break;
+
+ switch (params->loopback_mode) {
+ case ELINK_LOOPBACK_BMAC:
+ elink_init_bmac_loopback(params, vars);
+ break;
+ case ELINK_LOOPBACK_EMAC:
+ elink_init_emac_loopback(params, vars);
+ break;
+ case ELINK_LOOPBACK_XMAC:
+ elink_init_xmac_loopback(params, vars);
+ break;
+ case ELINK_LOOPBACK_UMAC:
+ elink_init_umac_loopback(params, vars);
+ break;
+ case ELINK_LOOPBACK_XGXS:
+ case ELINK_LOOPBACK_EXT_PHY:
+ elink_init_xgxs_loopback(params, vars);
+ break;
+ default:
+ if (!CHIP_IS_E3(sc)) {
+ if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
+ elink_xgxs_deassert(params);
+ else
+ elink_serdes_deassert(sc, params->port);
}
+ elink_link_initialize(params, vars);
+ DELAY(1000 * 30);
+ elink_link_int_enable(params);
+ break;
+ }
elink_update_mng(params, vars->link_status);
elink_update_mng_eee(params, vars->eee_status);
REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
}
-#ifdef ELINK_INCLUDE_EMUL
- /* Stop BigMac rx */
- if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
-#endif
- if (!CHIP_IS_E3(sc))
- elink_set_bmac_rx(sc, port, 0);
-#ifdef ELINK_INCLUDE_EMUL
- /* Stop XMAC/UMAC rx */
- if (!(params->feature_config_flags &
- ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
-#endif
- if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
- elink_set_xmac_rxtx(params, 0);
- elink_set_umac_rxtx(params, 0);
- }
+ if (!CHIP_IS_E3(sc))
+ elink_set_bmac_rx(sc, port, 0);
+ if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
+ elink_set_xmac_rxtx(params, 0);
+ elink_set_umac_rxtx(params, 0);
+ }
/* Disable emac */
if (!CHIP_IS_E3(sc))
REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
}
-#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
- if (!CHIP_REV_IS_SLOW(sc))
-#endif
- if (params->phy[ELINK_INT_PHY].link_reset)
- params->phy[ELINK_INT_PHY].link_reset(¶ms->
- phy
- [ELINK_INT_PHY],
- params);
+ if (params->phy[ELINK_INT_PHY].link_reset)
+ params->phy[ELINK_INT_PHY].link_reset(¶ms->
+ phy
+ [ELINK_INT_PHY],
+ params);
/* Disable nig ingress interface */
if (!CHIP_IS_E3(sc)) {
uint32_t phy_ver, val;
uint8_t phy_index = 0;
uint32_t ext_phy_type, ext_phy_config;
-#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
- if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
- return ELINK_STATUS_OK;
-#endif
elink_set_mdio_clk(sc, GRCBASE_EMAC0);
elink_set_mdio_clk(sc, GRCBASE_EMAC1);
*/
not_kr2_device = (((base_page & 0x8000) == 0) ||
(((base_page & 0x8000) &&
- ((next_page & 0xe0) == 0x2))));
+ ((next_page & 0xe0) == 0x20))));
/* In case KR2 is already disabled, check if we need to re-enable it */
if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
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