(((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
((vf)->version_minor == 1))
+static inline void
+I40E_WRITE_GLB_REG(struct i40e_hw *hw, uint32_t reg, uint32_t value) {
+ I40E_WRITE_REG(hw, reg, value);
+ PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
+ "with value 0x%08x",
+ reg, value);
+}
+
/* index flex payload per layer */
enum i40e_flxpld_layer_idx {
I40E_FLXPLD_L2_IDX = 0,
ETH_RSS_NONFRAG_IPV6_OTHER | \
ETH_RSS_L2_PAYLOAD)
+/* All bits of RSS hash enable for X722*/
+#define I40E_RSS_HENA_ALL_X722 ( \
+ (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
+ (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
+ (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
+ (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
+ (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
+ (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
+ I40E_RSS_HENA_ALL)
+
/* All bits of RSS hash enable */
#define I40E_RSS_HENA_ALL ( \
(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
/* Relative credits within same TC with respect to other VSIs or Comps */
uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
/* Bandwidth limit per TC */
- uint8_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
+ uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
/* Max bandwidth limit per TC */
uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
};
struct i40e_hw_port_stats stats_offset;
struct i40e_hw_port_stats stats;
+ /* internal packet byte count, it should be excluded from the total */
+ uint64_t internal_rx_bytes;
+ uint64_t internal_tx_bytes;
+ uint64_t internal_rx_bytes_offset;
+ uint64_t internal_tx_bytes_offset;
bool offset_loaded;
struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
bool floating_veb; /* The flag to use the floating VEB */
/* The floating enable flag for the specific VF */
bool floating_veb_list[I40E_MAX_VF];
+
+ bool support_multi_driver; /* 1 - support multiple driver */
};
enum pending_msg {
enum i40e_aq_link_speed link_speed;
bool vf_reset;
volatile uint32_t pend_cmd; /* pending command not finished yet */
- uint32_t cmd_retval; /* return value of the cmd response from PF */
+ int32_t cmd_retval; /* return value of the cmd response from PF */
u16 pend_msg; /* flags indicates events from pf not handled yet */
uint8_t *aq_resp; /* buffer to store the adminq response from PF */
struct rte_timecounter tx_tstamp_tc;
};
+enum I40E_WARNING_IDX {
+ I40E_WARNING_DIS_FLX_PLD,
+ I40E_WARNING_ENA_FLX_PLD,
+ I40E_WARNING_QINQ_PARSER,
+ I40E_WARNING_QINQ_CLOUD_FILTER,
+ I40E_WARNING_TPID,
+ I40E_WARNING_FLOW_CTL,
+ I40E_WARNING_GRE_KEY_LEN,
+ I40E_WARNING_QF_CTL,
+ I40E_WARNING_HASH_INSET,
+ I40E_WARNING_HSYM,
+ I40E_WARNING_HASH_MSK,
+ I40E_WARNING_FD_MSK,
+ I40E_WARNING_RPL_CLD_FILTER,
+};
+
int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
int i40e_vsi_release(struct i40e_vsi *vsi);
struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
struct i40e_vsi_vlan_pvid_info *info);
int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
-uint64_t i40e_config_hena(uint64_t flags);
+uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
uint64_t i40e_parse_hena(uint64_t flags);
enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
}
static inline uint16_t
-i40e_calc_itr_interval(int16_t interval)
+i40e_calc_itr_interval(int16_t interval, bool is_multi_drv)
{
- if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
- interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
+ if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
+ if (is_multi_drv)
+ interval = I40E_QUEUE_ITR_INTERVAL_MAX;
+ else
+ interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
+ }
/* Convert to hardware count, as writing each 1 represents 2 us */
return interval / 2;
}
+static inline void
+i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
+{
+ const char *warning;
+ static const char *const warning_list[] = {
+ [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
+ [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
+ [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
+ [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
+ [I40E_WARNING_TPID] = "support TPID configuration",
+ [I40E_WARNING_FLOW_CTL] = "configure water marker",
+ [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
+ [I40E_WARNING_QF_CTL] = "support hash function setting",
+ [I40E_WARNING_HASH_INSET] = "configure hash input set",
+ [I40E_WARNING_HSYM] = "set symmetric hash",
+ [I40E_WARNING_HASH_MSK] = "configure hash mask",
+ [I40E_WARNING_FD_MSK] = "configure fdir mask",
+ [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
+ };
+
+ warning = warning_list[idx];
+
+ RTE_LOG(WARNING, PMD,
+ "Global register is changed during %s\n",
+ warning);
+}
+
#define I40E_VALID_FLOW(flow_type) \
((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
(flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
+#define I40E_VALID_PCTYPE_X722(pctype) \
+ ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
+ (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
+ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
+ (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
+
#define I40E_VALID_PCTYPE(pctype) \
((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
(pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
(pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
+#define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
+ (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
+
+#define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
+ (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
+
#endif /* _I40E_ETHDEV_H_ */
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