New upstream version 16.11.3

[deb_dpdk.git] / drivers / net / i40e / i40e_ethdev.h

diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 61dfa93..f283319 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -149,6 +149,16 @@ enum i40e_flxpld_layer_idx {
        ETH_RSS_NONFRAG_IPV6_OTHER | \
        ETH_RSS_L2_PAYLOAD)
 
+/* All bits of RSS hash enable for X722*/
+#define I40E_RSS_HENA_ALL_X722 ( \
+       (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
+       (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
+       (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
+       (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
+       (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
+       (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
+       I40E_RSS_HENA_ALL)
+
 /* All bits of RSS hash enable */
 #define I40E_RSS_HENA_ALL ( \
        (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
@@ -217,7 +227,7 @@ struct i40e_bw_info {
        /* Relative credits within same TC with respect to other VSIs or Comps */
        uint8_t  bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
        /* Bandwidth limit per TC */
-       uint8_t  bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
+       uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
        /* Max bandwidth limit per TC */
        uint8_t  bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
 };
@@ -421,6 +431,11 @@ struct i40e_pf {
 
        struct i40e_hw_port_stats stats_offset;
        struct i40e_hw_port_stats stats;
+       /* internal packet byte count, it should be excluded from the total */
+       uint64_t internal_rx_bytes;
+       uint64_t internal_tx_bytes;
+       uint64_t internal_rx_bytes_offset;
+       uint64_t internal_tx_bytes_offset;
        bool offset_loaded;
 
        struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
@@ -517,7 +532,7 @@ struct i40e_vf {
        enum i40e_aq_link_speed link_speed;
        bool vf_reset;
        volatile uint32_t pend_cmd; /* pending command not finished yet */
-       uint32_t cmd_retval; /* return value of the cmd response from PF */
+       int32_t cmd_retval; /* return value of the cmd response from PF */
        u16 pend_msg; /* flags indicates events from pf not handled yet */
        uint8_t *aq_resp; /* buffer to store the adminq response from PF */
 
@@ -577,7 +592,7 @@ int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
                           struct i40e_vsi_vlan_pvid_info *info);
 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
-uint64_t i40e_config_hena(uint64_t flags);
+uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
 uint64_t i40e_parse_hena(uint64_t flags);
 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
@@ -701,6 +716,25 @@ i40e_calc_itr_interval(int16_t interval)
        (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
        (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
 
+#define I40E_VALID_PCTYPE_X722(pctype) \
+       ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
+       (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
+       (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
+       (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
+
 #define I40E_VALID_PCTYPE(pctype) \
        ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
        (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
@@ -714,4 +748,18 @@ i40e_calc_itr_interval(int16_t interval)
        (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
        (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
 
+#define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
+       (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
+
+#define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
+       (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
+
 #endif /* _I40E_ETHDEV_H_ */